SNVSBK8A October   2020  – March 2021 LM5157-Q1 , LM51571-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
      2. 9.3.2  High Voltage VCC Regulator (BIAS, VCC Pin)
      3. 9.3.3  Soft Start (SS Pin)
      4. 9.3.4  Switching Frequency (RT Pin)
      5. 9.3.5  Dual Random Spread Spectrum - DRSS (MODE Pin)
      6. 9.3.6  Clock Synchronization (UVLO/SYNC/EN Pin)
      7. 9.3.7  Current Sense and Slope Compensation
      8. 9.3.8  Current Limit and Minimum On Time
      9. 9.3.9  Feedback and Error Amplifier (FB, COMP Pin)
      10. 9.3.10 Power-Good Indicator (PGOOD Pin)
      11. 9.3.11 Hiccup Mode Overload Protection (MODE Pin)
      12. 9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
      13. 9.3.13 Internal MOSFET (SW Pin)
      14. 9.3.14 Overvoltage Protection (OVP)
      15. 9.3.15 Thermal Shutdown (TSD)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Shutdown Mode
      2. 9.4.2 Standby Mode
      3. 9.4.3 Run Mode
        1. Spread Spectrum Enabled
        2. Hiccup Mode Protection Enabled
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Recommended Components
        3. Inductor Selection (LM)
        4. Output Capacitor (COUT)
        5. Input Capacitor
        6. Diode Selection
      3. 10.2.3 Application Curve
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. Custom Design With WEBENCH® Tools
      3. 13.1.3 Export Control Notice
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-BCF7C7AE-4F05-4061-A9ED-6F736DAF473B-low.gif Figure 7-1 16-Pin WQFN With Wettable Flanks RTE Package (Top View)
Table 7-1 Pin Functions
1, 16 PGND P Power ground pin. Source connection of the internal N-channel power MOSFET
2 VCC P Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver. Connect a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor from this pin to PGND.
3 BIAS P Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
4 PGOOD O Power-good indicator. An open-drain output that goes low if FB is below the undervoltage threshold (VUVTH). Connect a pullup resistor to the system voltage rail.
5 RT I Switching frequency setting pin. The switching frequency is programmed by a single resistor between RT and AGND.
6 UVLO/SYNC/EN I Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN).
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be programmed by connecting this pin to the supply voltage through a voltage divider. If a programmable UVLO is used, connect the low-side UVLO resistor to AGND. This pin must not be left floating. Connect to the BIAS pin if not used.
External synchronization clock input pin. The internal clock can be synchronized to an external clock by applying a negative pulse signal into the pin.
7 AGND G Analog ground pin. Connect to the analog ground plane through a wide and short path.
8 COMP O Output of the internal transconductance error amplifier. Connect the loop compensation components between this pin and AGND.
9 FB I Inverting input of the error amplifier. Connect a voltage divider to set output voltage in boost, SEPIC, or primary-side regulated flyback topologies. Connect the low-side feedback resistor close to AGND.
10 SS I Soft-start time programming pin. An external capacitor and an internal current source set the ramp rate of the internal error amplifier reference during soft start. Connect the ground connection of the capacitor to AGND.
11 MODE I MODE = 0 V or connect to AGND during initial power up. Hiccup mode protection is disabled and spread spectrum is disabled.
MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up. Hiccup mode protection is enabled and spread spectrum is enabled.
MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up. Hiccup mode protection is enabled and spread spectrum is disabled.
MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up. Hiccup mode protection is disabled and spread spectrum is enabled.
12, 13, 14 SW Switch pin. Drain connection of the internal N-channel power MOSFET
15 NC No internal electrical contact. Optionally connect to PGND for improved thermal conductivity.
EP Exposed pad of the package. The exposed pad must be connected to AGND and the large ground copper plane to decrease thermal resistance.
G = Ground, I = Input, O = Output, P = Power