SNVSAJ3B March 2016 – February 2017 LM5165Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The LM5165Q1 only requires a few external components to convert from a wide range of supply voltages to a fixed output voltage. To expedite and streamline the process of designing of a LM5165Q1based converter, a comprehensive LM5165Q1 Quickstart design tool is available for download to assist the designer with component selection for a given application. WEBENCH® online software is also available to generate complete designs, leveraging iterative design procedures and access to comprehensive component databases. The following sections discuss the design procedure for both COT and PFM modes using specific circuit design examples.
As mentioned previously, the LM5165Q1 also integrates several optional features to meet system design requirements, including precision enable, UVLO, programmable soft start, programmable switching frequency in COT mode, adjustable current limit, and PGOOD indicator. Each application incorporates these features as needed for a more comprehensive design. The application circuits detailed below show LM5165Q1 configuration options suitable for several application use cases. Refer to the LM5165EVMHDC50X and LM5165EVMHDP50A EVM user's guides for more detail.

For stepbystep design procedure, circuit schematics, bill of materials, PCB files, simulation and test results of an LM5165powered implementation, refer to Field Transmitter with Bluetooth® Low Energy Connectivity Powered from 4 to 20mA Current Loop reference design. 
The schematic diagram of a 5V, 150mA COT converter is given in Figure 37.
The target fullload efficiency is 91% based on a nominal input voltage of 12 V and an output voltage of 5 V. The required input voltage range is 5 V to 65 V. The LM5165XQ1 is chosen to deliver a fixed 5V output voltage. The switching frequency is set by resistor R_{RT} at 220 kHz. The output voltage softstart time is 6 ms. The required components are listed in Table 2.
REF DES  QTY  SPECIFICATION  VENDOR  PART NUMBER 

C_{IN}  1  1 µF, 100 V, X7R, 1206 ceramic  TDK  C3216X7R2A105K160AA 
C_{OUT}  1  22 µF, 10 V, X7R, 1206 ceramic  Murata  GRM31CR71A226KE15L 
L_{F}  1  220 µH ±20%, 0.29 A, 0.92 Ω typ DCR, 5.8 x 5.8 x 2.8 mm  Würth Electronik  WETPC 5828 744053221 
220 µH ±30%, 0.3 A, 1.25 Ω max DCR, 5.8 x 5.8 x 3.0 mm  Bourns  SRR5028221Y  
R_{ESR}  1  1.5 Ω, 5%, 0402  Std  Std 
R_{}_{RT}  1  133 kΩ, 1%, 0402  Std  Std 
C_{SS}  1  47 nF, 10 V, X7R, 0402 ceramic  Std  Std 
U_{1}  1  LM5165XQ1 Synchronous Buck Converter, VSON10, 5V Fixed  TI  LM5165XQDRCRQ1 
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As mentioned, the switching frequency of a COTconfigured LM5165Q1 is set by the ontime programming resistor at the RT pin. As shown by Equation 2, a standard 1% resistor of 133 kΩ gives a switching frequency of 230 kHz.
Note that at very low duty cycles, the minimum controllable ontime of the highside MOSFET, T_{ON(min)}, of 180 ns may affect choice of switching frequency. In CCM, T_{ON(min)} limits the voltage conversion stepdown ratio for a given switching frequency. The minimum controllable duty cycle is given by Equation 9:
Given a fixed T_{ON(min)}, it follows that higher switching frequency implies a larger minimum controllable duty cycle. Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range, solution size and efficiency. The maximum supply voltage for a given T_{ON(min)} before switching frequency reduction occurs is given by Equation 10.
The inductor ripple current (assuming CCM operation) and peak inductor current are given respectively by Equation 11 and Equation 12.
For most applications, choose an inductance such that the inductor ripple current, ΔI_{L}, is between 30% and 50% of the rated load current at nominal input voltage. Calculate the inductance using Equation 13.
Choosing a 220µH inductor in this design results in 55mA peaktopeak ripple current at nominal input voltage of 12 V, equivalent to 37% of the 150mA rated load current. The peak inductor current at maximum input voltage of 65 V is 195 mA, sufficiently below the LM5165Q1 peak current limit of 240 mA.
Check the inductor datasheet to ensure that the inductor's saturation current is well above the current limit setting of a particular design. Ferrite designs have low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. However, ferrite core materials exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that inductor saturation current generally deceases as the core temperature increases.
Select the output capacitor to limit the capacitive voltage ripple at the converter output. This is the sinusoidal ripple voltage that arises from the triangular ripple current flowing in the capacitor. Select an output capacitance using Equation 14 to limit the voltage ripple component to 0.5% of the output voltage.
Substituting ΔI_{L(nom)} of 55 mA gives C_{OUT} greater than 5 μF. Mindful of the voltage coefficient of ceramic capacitors, select a 22µF, 10V capacitor with X7R dielectric in 1206 footprint.
Select a series resistor such that sufficient ripple in phase with the SW node voltage appears at the feedback node, FB. Use Equation 15 to calculate the required ripple resistance, designated R_{ESR}.
With V_{OUT} of 5 V, V_{REF} of 1.223 V, and ΔI_{L(nom)} of 55 mA at the nominal input voltage of 12 V, the required R_{ESR} is 1.5 Ω. Calculate the total output voltage ripple in CCM using Equation 16.
An input capacitor is necessary to limit the input ripple voltage while providing switchingfrequency AC current to the buck power stage. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the VIN and GND pins of the LM5165Q1. The input capacitors conduct a squarewave current of peaktopeak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESRrelated ripple component, the peaktopeak ripple voltage amplitude is given by Equation 17.
The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔV_{IN}, is given by Equation 18.
The recommended highfrequency capacitance is 1 µF or higher and should be a highquality ceramic type X5R or X7R with sufficient voltage rating. Based on the voltage coefficient of ceramic capacitors, choose a voltage rating of twice the maximum input voltage. Additionally, some bulk capacitance is required if the LM5165Q1 circuit is not located within approximately 5 cm from the input voltage source. This capacitor provides damping to the resonance associated with parasitic inductance of the supply lines and highQ ceramics.
Connect an external softstart capacitor for a specific softstart time. In this example, select a softstart capacitance of 47 nF based on Equation 8 to achieve a softstart time of 6 ms.
Unless otherwise stated, application performance curves were taken at T_{A} = 25°C.
V_{OUT} = 5 V 
V_{IN} = 13.5 V I_{OUT} = 100 mA 
L_{IN} = 22 µH C_{IN(EXT)} = 10 µF 
V_{IN} = 12 V  I_{OUT} = 150 mA 
V_{IN} stepped to 24 V  30Ω Load 
V_{IN} brownout to 3.2 V 
V_{IN} = 24 V 
V_{IN} = 12 V  I_{OUT} = 0 mA 
V_{IN} = 5.7 V  I_{OUT} = 150 mA 
V_{IN} = 24 V  30Ω Load 
V_{IN} brownout to 3.2 V 
I_{OUT} = 150 mA 
The schematic diagram of a 3.3V, 50mA PFM converter with minimum component count is given in Figure 50.
The target fullload efficiency of this design is 88% based on a nominal input voltage of 12 V and an output voltage of 3.3 V. The required total input voltage range is 3.5 V to 65 V. The LM5165Q1 has an internallyset softstart time of 900 µs and an adjustable peak current limit threshold. The BOM is listed in Table 3.
REF DES  QTY  SPECIFICATION  VENDOR  PART NUMBER 

C_{IN}  1  1 µF, 100 V, X7S, 0805 ceramic  TDK  C2012X7S2A474M125AE 
C_{OUT}  1  10 µF, 6.3 V, X7R, 0805 ceramic  Taiyo Yuden  JMK212AB7106KGT 
Murata  GRM21BR70J106KE76K  
L_{F}  1  47 µH ±20%, 0.56 A, 650 mΩ maximum DCR, 3.9 × 3.9 × 1.7 mm  Coilcraft  LPS4018473MRC 
47 µH ±20%, 0.7 A, 620 mΩ typical DCR, 4.0 × 4.0 × 1.8 mm  Würth  74404042470  
47 µH ±20%, 0.57 A, 650 mΩ typical DCR, 4.0 × 4.0 × 1.8 mm  Taiyo Yuden  NR4018T470M  
R_{}_{ILIM}  1  56.2 kΩ, 1%, 0402  Std  Std 
U_{1}  1  LM5165YQ1 Synchronous Buck Converter, VSON10, 3.3V Fixed  TI  LM5165YQDRCRQ1 
Install a 56.2kΩ resistor from ILIM to GND to select a 120mA peak current limit threshold setting to meet the rated output current of 50 mA.
Tie RT to GND to select PFM mode of operation. The inductor, input voltage, output voltage, and peak current determine the pulse switching frequency of a PFMconfigured LM5165Q1. For a given input voltage, output voltage and peak current, the inductance of L_{F} sets the switching frequency when the output is in regulation. Use Equation 19 to select an inductance of 47 µH based on the target PFM converter switching frequency of 350 kHz at 12V input.
I_{PK(PFM)} in this example is the peak current limit setting of 120 mA plus an additional 10% margin added to include the effect of the 100ns peak current comparator delay. An additional constraint on the inductance is the 180ns minimum ontime of the highside MOSFET. Therefore, to keep the inductor current well controlled, choose an inductance that is larger than L_{F(min)} using Equation 20 where V_{IN(max)} is the maximum input supply voltage for the application, t_{ON(min)} is 180 ns, and I_{L(max)} is the maximum allowed peak inductor current.
Choose an inductor with saturation current rating above the peak current limit setting, and allow for derating of the saturation current at the highest expected operating temperature.
The output capacitor, C_{OUT}, filters the inductor’s ripple current and stores energy to meet the load current requirement when the LM5165Q1 is in sleep mode. The output ripple has a base component of amplitude V_{OUT}/123 related to the 10mV typical feedback comparator hysteresis in PFM. The wakeup time from sleep to active mode adds a ripple voltage component that is a function of the output current. Approximate the total output ripple by Equation 21.
Also, the output capacitance must be large enough to accept the energy stored in the inductor without a large deviation in output voltage. Setting this voltage change equal to 0.5% of the output voltage results in:
In general, select the capacitance of C_{OUT} to limit the output voltage ripple at full load current, ensuring that it is rated for worstcase RMS ripple current given by I_{RMS} = I_{PK(PFM)}/2. In this design example, choose a 10µF, 6.3V ceramic output capacitor with X7R dielectric and 0805 footprint.
The input capacitor, C_{IN}, filters the highside MOSFET's triangular current waveform, see Figure 72. To prevent large ripple voltage, use a lowESR ceramic input capacitor sized for the worstcase RMS ripple current given by I_{RMS} = I_{OUT}/2. In this design example, choose a 1µF, 100V ceramic input capacitor with X7S dielectric and 0805 footprint.
V_{OUT} = 3.3 V 
V_{IN} stepped to 12 V  66Ω Load 
V_{IN} = 12 V 
V_{IN} = 12 V  I_{OUT} = 50 mA 
V_{IN} = 12 V  66Ω Load 
I_{OUT} = 50 mA 
The schematic diagram of 12V, 75mA PFM converter is given in Figure 57.
The fullload efficiency specification is 92% based on a nominal input voltage of 24 V and an output voltage of 12 V. The total input voltage range is 18 V to 65 V, with UVLO turnon and turnoff at 16 V and 14.5 V, respectively. The output voltage setpoint is established by feedback resistors, R_{FB1} and R_{FB2}. The switching frequency is set by inductor L_{F} at 500 kHz at nominal input voltage. The required components are listed in Table 4.
REF DES  QTY  SPECIFICATION  VENDOR  PART NUMBER 

C_{IN}  1  1 µF, 100 V, X7S, 0805 ceramic  Murata  GRJ21BC72A105KE11L 
1 µF, 100 V, X7S, 0805 ceramic, AECQ200  TDK  CGA4J3X7S2A105K125AE  
C_{OUT}  1  10 µF, 16 V, X7R, 0805 ceramic  Taiyo Yuden  EMK212BB7106MGT 
10 µF, 16 V, X7R, 0805 ceramic, AECQ200  TDK  CGA4J1X7S1C106K125AC  
L_{F}  1  47 µH ±20%, 0.56 A, 650 mΩ maximum DCR, 3.9 × 3.9 × 1.7 mm AECQ200 
Coilcraft  LPS4018473MRC 
R_{}_{ILIM}  1  24.9 kΩ, 1%, 0402  Std  Std 
R_{}_{FB1}  1  1 MΩ, 1%, 0402  Std  Std 
R_{}_{FB2}  1  113 kΩ, 1%, 0402  Std  Std 
R_{}_{UV1}  1  10 MΩ, 1%, 0603  Std  Std 
R_{}_{UV2}  1  825 kΩ, 1%, 0402  Std  Std 
R_{}_{HYS}  1  37.4 kΩ, 1%, 0402  Std  Std 
C_{}_{SS}  1  22 nF, 10 V, X7R, 0402  Std  Std 
U_{1}  1  LM5165Q1 Synchronous Buck Converter, VSON10, 3 mm × 3 mm  TI  LM5165QDRCRQ1 
The component selection procedure for this PFM design is quite similar to that of Design 2, see Figure 50.
Install a 24.9kΩ resistor from ILIM to GND to select the 180mA peak current limit setting for a rated output current of 75 mA.
Tie RT to GND to select PFM mode of operation. Set the switching frequency by the filter inductance, L_{F}. Calculate an inductance of 47 µH based on the target PFM converter switching frequency of 500 kHz at 24V input using Equation 19. Use a peak current limit setting, I_{PK(PFM)}, of 180 mA plus an additional 50% margin in this highfrequency design to include the effect of the 100ns current limit comparator delay. Choose an inductor with saturation current rating well above the peak current limit setting, and allow for derating of the saturation current at the highest expected operating temperature.
Choose a 1µF, 100V ceramic input capacitor with 0805 footprint. Such a capacitor is typically available in X5R or X7S dielectric. Based on Equation 22, select a 10µF, 16V ceramic output capacitor with X7R dielectric and 0805 footprint.
The output voltage of the LM5165Q1 is externally adjustable using a resistor divider network. The divider network comprises the upper feedback resistor R_{FB1} and lower feedback resistor R_{FB2}. Select R_{FB1} of 1 MΩ to minimize quiescent current and improve lightload efficiency in this application. With the desired output voltage setpoint of 12 V and V_{FB} = 1.223 V, calculate the resistance of R_{FB2} using Equation 5 as 113.5 kΩ. Choose the closest available standard value of 113 kΩ for R_{FB2}. Please refer to Adjustable Output Voltage (FB) for more detail.
Adjust the undervoltage lockout (UVLO) using an externallyconnected resistor divider network of R_{UV1}, R_{UV2}, and R_{HYS}. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brownouts when the input voltage is falling. The EN rising threshold for the LM5165Q1 is 1.212 V.
Rearranging Equation 6 and Equation 7, the expressions to calculate R_{UV2} and R_{HYS} are as follows:
Choose R_{UV1} as 10 MΩ to minimize input quiescent current. Given the desired input voltage UVLO thresholds of 16 V and 14.5 V, calculate the resistance of R_{UV2} and R_{HYS} as 825 kΩ and 37.4 kΩ, respectively. See Precision Enable (EN) and Hysteresis (HYS) for more detail.
Install a 22nF capacitor from SS to GND for a softstart time of 3 ms.
V_{OUT} = 12 V 
V_{IN} = 24 V  I_{OUT} = 75 mA 
V_{IN} stepped to 24 V  160Ω Load 
V_{IN} = 24 V  I_{OUT} = 0 mA 
The schematic diagram of a 3.3V, 150mA COT converter is given in Figure 62.
The target fullload efficiency is 91% based on a nominal input voltage of 24 V and an output voltage of 3.3 V. The required input voltage range is 3 V to 65 V. The LM5165YQ1 is chosen to deliver a fixed 3.3V output voltage. The switching frequency is set by resistor R_{RT} at approximately 160 kHz. The output voltage softstart time is 4 ms. The required components are listed in Table 5. The component selection procedure for this COT design is quite similar to that of Design 1, see Figure 37.
REF DES  QTY  SPECIFICATION  VENDOR  PART NUMBER 

C_{IN}  1  1 µF, 100 V, X7R, 1206 ceramic  Murata  GRM31CR72A105KA01L 
C_{OUT}  1  22 µF, 6.3 V, X7S, 0805 ceramic  Murata  GRM21BR660J226ME39K 
L_{F}  1  150 µH ±20%, 0.29 A, 0.86 Ω typical DCR, 4.8 × 4.8 × 2.9 mm  Coilcraft  LPS5030154MLC 
R_{ESR}  1  0.5 Ω, 5%, 0402  Std  Std 
R_{}_{RT}  1  121 kΩ, 1%, 0402  Std  Std 
C_{SS}  1  33 nF, 10 V, X7R, 0402 ceramic  Std  Std 
U_{1}  1  LM5165YQ1 Synchronous Buck Converter, VSON10, 3.3V Fixed  TI  LM5165YQDRCRQ1 
V_{IN} = 24 V  I_{OUT} = 150 mA 
The schematic diagram of a 15V, 150mA COT converter is given in Figure 65.
The target fullload efficiency is 92% based on a nominal input voltage of 36 V and an output voltage of 15 V. The input voltage operating range is 24 V to 48 V, but transients as high as 65 V are possible in the application. UVLO turnon and turnoff are set at 19 V and 17 V, respectively. The LM5165Q1 switching frequency is set at approximately 600 kHz by resistor R_{RT} of 143 kΩ. The output voltage softstart time is 6 ms. The required components are listed in Table 6. The component selection procedure for this COT design is quite similar to that of Design 1, see Figure 37.
REF DES  QTY  SPECIFICATION  VENDOR  PART NUMBER 

C_{IN}  1  1 µF, 100 V, X7R, 1206 ceramic  AVX  12061C105KAT2A 
C_{OUT}  1  10 µF, 25 V, X7R, 1206 ceramic  Taiyo Yuden  TMK316B7106KLTD 
L_{F}  1  150 µH ±20%, 0.29 A, 0.86 Ω typical DCR, 4.8 × 4.8 × 2.9 mm  Coilcraft  LPS5030154MLC 
R_{ESR}  1  2.2 Ω, 5%, 0402  Std  Std 
R_{}_{RT}  1  143 kΩ, 1%, 0402  Std  Std 
R_{}_{FB1}  1  499 kΩ, 1%, 0402  Std  Std 
R_{}_{FB2}  1  44.2 kΩ, 1%, 0402  Std  Std 
R_{}_{UV1}  1  10 MΩ, 1%, 0603  Std  Std 
R_{}_{UV2}  1  681 kΩ, 1%, 0402  Std  Std 
R_{}_{HYS}  1  40.2 kΩ, 1%, 0402  Std  Std 
C_{FF}  1  10 pF, 10 V, X7R, 0402 ceramic  Std  Std 
C_{SS}  1  47 nF, 10 V, X7R, 0402 ceramic  Std  Std 
U_{1}  1  LM5165Q1 Synchronous Buck Converter, VSON10, 3 mm × 3 mm  TI  LM5165QDRCRQ1 
Depending on the required ripple resistance when operating in COT mode, the resultant output voltage ripple may be deemed too high for a given application. One option is to place a feedforward capacitor C_{FF} in parallel with the upper feedback resistor R_{FB1}. Capacitor C_{FF} increases the highfrequency gain from V_{OUT} to V_{FB} close to unity such that the output voltage ripple couples directly to the FB node.
V_{OUT} = 15 V 
V_{IN} = 36 V  I_{OUT} = 150 mA 
V_{IN} = 36 V 
V_{IN} stepped to 36 V  I_{OUT} = 150 mA 
V_{IN} = 36 V  I_{OUT} = 0 mA 
V_{IN} = 36 V 