SNVSBZ3 June   2021 LM5168-Q1

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Internal Soft Start
      4. 8.3.4  On-Time Generator
      5. 8.3.5  Current Limit
      6. 8.3.6  N-Channel Buck Switch and Driver
      7. 8.3.7  Synchronous Rectifier
      8. 8.3.8  Enable/Undervoltage Lockout (EN/UVLO)
      9. 8.3.9  Power Good (PGOOD)
      10. 8.3.10 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Sleep Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency (RT)
        2. 9.2.2.2  Transformer Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Secondary Output Diode
        5. 9.2.2.5  Regulation Comparator
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Type-3 Ripple Network
        8. 9.2.2.8  Minimum Secondary Output Load
        9. 9.2.2.9  Example Design Summary
        10. 9.2.2.10 Thermal Considerations
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Control Architecture

The LM516x-Q1 step-down switching converter employs a constant on-time (COT) control scheme. The COT control scheme sets a fixed on time, tON, of the high-side FET using a timing resistor (RT). tON is adjusted as VIN changes and is inversely proportional to the input voltage to maintain a fixed frequency when in Continuous Conduction mode (CCM). After expiration of tON, the high-side FET remains off until the feedback pin is equal or below the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple voltage that is in-phase with the inductor current during the off time. Furthermore, this change in feedback voltage during the off time must be large enough to dominate any noise present at the feedback node. The minimum recommended ripple voltage is 20 mV. See Table 8-1 for different types of ripple injection schemes that ensure stability over the full input voltage range.

During a rapid start-up or a positive load step, the regulator operates with minimum off times until regulation is achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot. When regulating the output in steady-state operation, the off time automatically adjusts itself to produce the SW pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the switching frequency FSW is programmed by the RT resistor. Use Equation 1 to calculate the switching frequency.

Equation 1. FSW(kHz)=2500*VOUT(V)RT(k)
Table 8-1 Ripple Generation Methods
TYPE 1TYPE 2TYPE 3
Lowest CostReduced RippleMinimum Ripple
GUID-20201221-CA0I-ZKC3-J9BZ-6MQQ71SVNWFN-low.gif
GUID-20201221-CA0I-FHPT-TMQ0-RT7RCFTVW82Z-low.gif
GUID-20201221-CA0I-LWTK-WSM1-BZHVC7ZXSV9K-low.gif
Equation 2. GUID-DC953535-2C50-4B74-B846-81C6FB5AEC38-low.gif
Equation 3. GUID-9E1DC1F8-82C5-4D4B-B4C1-F5712C6232C5-low.gif
Equation 4. GUID-90900BA0-463F-45CD-B6D8-951AC47F6210-low.gif
Equation 5. GUID-9E1DC1F8-82C5-4D4B-B4C1-F5712C6232C5-low.gif
Equation 6. GUID-87AA7DAE-A1E2-401B-939D-47124D427E28-low.gif
Equation 7. GUID-60890FD2-1332-4E84-848C-D9B0CF95C61C-low.gif
Equation 8. GUID-395CB235-0CB2-44EF-AF36-65DE351221C8-low.gif
Equation 9. GUID-5946B997-A0A1-4003-B381-5EF343B783F3-low.gif

Table 8-1 presents three different methods for generating appropriate voltage ripple at the feedback node. The Type-1 ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated voltage ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and through series resistance RESR. The capacitive ripple component is out of phase with the inductor current and does not decrease monotonically during the off time. The resistive ripple component is in-phase with the inductor current and decreases monotonically during the off time. The resistive ripple must exceed the capacitive ripple at VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off time. Equation 2 and Equation 3 define the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback node.

Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple, are reduced by a factor of VOUT / VFB1.

Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the feedback node with capacitor CB. Since this circuit does not use output voltage ripple, it is suited for applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details on this topic.

Light load mode operation can be set to PFM and DEM operation or FPWM operation as a factory option. Diode Emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current reduces switching loss, and prevents negative current conduction reduces conduction loss. Power conversion efficiency is higher in a DEM converter than an equivalent Forced-PWM CCM converter. With DEM operation, the duration that both power MOSFETs remain off progressively increases as load current decreases. When this idle duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA quiescent current from the input. In FPWM operation, the DEM feature is turned off. This means that the device remains in CCM under light loads, and the device is capable of operating in a fly-buck configuration.