SNVSBZ3 June 2021 LM5168-Q1
ADVANCE INFORMATION
The LM516x-Q1 step-down switching converter employs a constant on-time (COT) control scheme. The COT control scheme sets a fixed on time, t_{ON}, of the high-side FET using a timing resistor (R_{T}). t_{ON} is adjusted as V_{IN} changes and is inversely proportional to the input voltage to maintain a fixed frequency when in Continuous Conduction mode (CCM). After expiration of t_{ON}, the high-side FET remains off until the feedback pin is equal or below the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple voltage that is in-phase with the inductor current during the off time. Furthermore, this change in feedback voltage during the off time must be large enough to dominate any noise present at the feedback node. The minimum recommended ripple voltage is 20 mV. See Table 8-1 for different types of ripple injection schemes that ensure stability over the full input voltage range.
During a rapid start-up or a positive load step, the regulator operates with minimum off times until regulation is achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot. When regulating the output in steady-state operation, the off time automatically adjusts itself to produce the SW pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the switching frequency F_{SW} is programmed by the R_{T} resistor. Use Equation 1 to calculate the switching frequency.
TYPE 1 | TYPE 2 | TYPE 3 |
---|---|---|
Lowest Cost | Reduced Ripple | Minimum Ripple |
Equation 2. Equation 3. | Equation 4. Equation 5. Equation 6. | Equation 7. Equation 8.
Equation 9. |
Table 8-1 presents three different methods for generating appropriate voltage ripple at the feedback node. The Type-1 ripple generation method uses a single resistor, R_{ESR}, in series with the output capacitor. The generated voltage ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and through series resistance R_{ESR}. The capacitive ripple component is out of phase with the inductor current and does not decrease monotonically during the off time. The resistive ripple component is in-phase with the inductor current and decreases monotonically during the off time. The resistive ripple must exceed the capacitive ripple at V_{OUT} for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT converters, with multiple on-time bursts in close succession followed by a long off time. Equation 2 and Equation 3 define the value of the series resistance R_{ESR} to ensure sufficient in-phase ripple at the feedback node.
Type-2 ripple generation uses a C_{FF} capacitor in addition to the series resistor. As the output voltage ripple is directly AC-coupled by C_{FF} to the feedback node, the R_{ESR} and ultimately the output voltage ripple, are reduced by a factor of V_{OUT} / V_{FB1}.
Type-3 ripple generation uses an RC network consisting of R_{A} and C_{A}, and the switch node voltage to generate a triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the feedback node with capacitor C_{B}. Since this circuit does not use output voltage ripple, it is suited for applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details on this topic.
Light load mode operation can be set to PFM and DEM operation or FPWM operation as a factory option. Diode Emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current reduces switching loss, and prevents negative current conduction reduces conduction loss. Power conversion efficiency is higher in a DEM converter than an equivalent Forced-PWM CCM converter. With DEM operation, the duration that both power MOSFETs remain off progressively increases as load current decreases. When this idle duration exceeds 15 μs, the converter transitions into an ultra-low I_{Q} mode, consuming only 10-μA quiescent current from the input. In FPWM operation, the DEM feature is turned off. This means that the device remains in CCM under light loads, and the device is capable of operating in a fly-buck configuration.