SNVSBZ3 June   2021 LM5168-Q1

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Architecture
      2. 8.3.2  Internal VCC Regulator and Bootstrap Capacitor
      3. 8.3.3  Internal Soft Start
      4. 8.3.4  On-Time Generator
      5. 8.3.5  Current Limit
      6. 8.3.6  N-Channel Buck Switch and Driver
      7. 8.3.7  Synchronous Rectifier
      8. 8.3.8  Enable/Undervoltage Lockout (EN/UVLO)
      9. 8.3.9  Power Good (PGOOD)
      10. 8.3.10 Thermal Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Switching Frequency (RT)
        2. 9.2.2.2  Transformer Selection
        3. 9.2.2.3  Output Capacitor Selection
        4. 9.2.2.4  Secondary Output Diode
        5. 9.2.2.5  Regulation Comparator
        6. 9.2.2.6  Input Capacitor
        7. 9.2.2.7  Type-3 Ripple Network
        8. 9.2.2.8  Minimum Secondary Output Load
        9. 9.2.2.9  Example Design Summary
        10. 9.2.2.10 Thermal Considerations
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact PCB Layout for EMI Reduction
      2. 11.1.2 Feedback Resistors
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.8 Enable/Undervoltage Lockout (EN/UVLO)

The LM516x-Q1 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the converter is in a low-current Shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in Standby mode. In Standby mode, the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the rising threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the minimum operating voltage of the regulator. Use Equation 12 and Equation 13 to calculate the input UVLO turn-on and turn-off voltages, respectively.

Equation 12. GUID-01272282-2BF2-4A81-AC0C-0C010EB8298F-low.gif
Equation 13. GUID-5BE787B8-D26B-480E-9928-D17EC8FDF5C1-low.gif

TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN. If EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are active.