SNVSAQ6D November   2016  – August 2021 LM5170-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-DE96C59B-807B-44BF-BF39-4ABA0DEA9336-low.gif Figure 6-1 PHP Package48-Pin TQFPTop View
Table 6-1 Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
1 CSA2 I CH-2 differential current sense inputs. The CSA2 pin connects to the CH-2 power inductor. The CSB2 pin connects to the circuit breaker or directly to the LV-Port if the circuit breaker is not used. The CH-2 current sense resistor is placed between these two pins.
2 CSB2 I
3 NC — No Connect
4 VINX O Internally connected to VIN pin through a cutoff switch. When the controller is shutdown, VINX is disconnected from VIN, opening the current leakage path. When the controller is enabled, VINX is connected to VIN and serves as the pullup supply for the RC ramp generators at the RAMP1 and RAMP2 pins. VINX also pulls up the OVPA pin through an internal 3-MΩ resistor.
5 NC — No Connect
6 VIN I The input pin connecting to the HV-Port line voltage. It supplies the BRKG pin through an internal 330-µA current source.
7 NC — No Connect
8 RAMP2 I The inverting input of the CH-2 PWM Comparator. An external RC circuit tied between VINX, RAMP2, and AGND forms the ramp generator producing a ramp signal proportional to the HV-Port voltage, thus achieving a voltage feedforward function. The RAMP2 capacitor voltage is reset to AGND at the end of every switching cycle.
9 OVPA I Connected to the noninverting input of the HV-Port overvoltage comparator. An internal 3-MΩ pullup resistor and an external resistor across the OVPA and AGND pins form a divider that senses the HV-Port voltage. When the OVPA pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage condition is removed.
10 ULVO I The UVLO pin serves as the master enable pin. When UVLO is pulled below 1.25 V, the entire LM5170-Q1 is in a low quiescent current shutdown mode. When UVLO is pulled above 1.25 V but below 2.5 V, the LM5170-Q1 enters the initialization stage in which the nFAULT pin is first pulled up to 5 V, while the rest of the LM5170-Q1 is kept in the OFF state. When UVLO is pulled above the 2.5 V, the LM5170-Q1 enters a MOSFET failure detection stage. If no failure is detected, the circuit breaker gate driver (BRKS and BRKG) turns on, and the LM5170-Q1 enables the oscillator and RAMP generator, and stands by until the EN1 and EN2 commands enable the channel.
11 COMP2 O Output of the CH-2 transconductance (gm) error amplifier and the noninverting input of the CH-2 PWM comparator. A loop compensation network must be connected to this pin.
12 SS I The soft-start programming pin. An external capacitor and an internal 25-μA current source set the ramp rate of the COMP pins voltage during soft start. If CH-2 is enabled after CH-1 completes soft start, the CH-2 turnon will not be controlled by the SS pin.
13 SW2 I CH-2 switch node. Connect to the CH-2 high-side MOSFET source, the low-side MOSFET drain, and the bootstrap capacitor return terminal.
14 HB2 P CH-2 high-side gate driver bootstrap supply input
15 HO2 I/O CH-2 high-side gate driver output
16 NC — No Connect
17 LO2 I/O CH-2 low-side gate driver output
18 PGND G Power ground connection pin for the low-side gate drivers and external VCC bias supply
19 VCC I/P VCC bias supply pin, powering the drivers. An external bias supply between 9 V to 12 V must be applied across the VCC and PGND pins.
20 LO1 I/O CH-1 low-side gate driver output
21 NC — No Connect
22 HO1 I/O CH-1 high-side gate driver output
23 HB1 P CH-1 high-side gate driver bootstrap supply input
24 SW1 I CH-1 switch node. Connect to the CH-1 high-side MOSFET source, the low-side MOSFET drain, and the bootstrap capacitor return terminal.
25 OVPB I Connected to the noninverting input of the LV-Port overvoltage comparator. An internal 1-MΩ pullup resistor and an external resistor across the OVPB and AGND pins form the divider that senses the LV-Port voltage. When the converter operates in Boost mode the OVPB pin status is ignored. In Buck mode, when the OVPB pin voltage is above the 1.185-V threshold, the SS capacitor is discharged and held low until the overvoltage condition is removed.
26 COMP1 O Output of the CH-1 trans-conductance (gm) error amplifier and the noninverting input of the CH-1 PWM comparator. A loop compensation network must be connected to this pin.
27 nFAULT I/O Fault flag pin or external shutdown pin. When a MOSFET drain-to-source short circuit failure is detected before start-up, the nFAULT pin is internally pulled low to report the short-circuit failure, and the LM5170-Q1 will remain in a disabled state. The nFAULT pin can also be externally pulled low to shut down the LM5170-Q1, serving as a forced shutdown pin. In forced shutdown, all gate drivers turn off, and nFAULT is latched low until the UVLO pin is pulled below 1.25 V to release the latch and initiate a new start-up.
28 RAMP1 I The inverting input of the CH-1 PWM comparator. An external RC circuit tied between VINX, RAMP1, and AGND forms the ramp generator producing a ramp signal proportional to the HV-Port voltage, thus achieving a voltage feedforward function. The RAMP1 capacitor voltage is reset to AGND at the end of every switching cycle.
29 OPT I Multiphase configuration pin. Tied to either VCCA or AGND, the OPT pin sets the phase lag of the SYNCOUT signal corresponding to 4 phase or 3 phase operation, respectively.
30 IPK I A resistor connected between IPK and AGND sets the threshold for the cycle-by-cycle current limit comparator
31 VCCA I/P Analog bias supply pin. Connect VCCA to VCC through an external 25-Ω resistor. A low-pass filter capacitor is required from the VCCA pin to AGND.
32 NC — No Connect
33 BRKS O Connect to the common source of the circuit breaker MOSFET pair. When the circuit breaker function is disabled, simply connect to AGND through a 20-kΩ resistor.
34 BRKG O Connect to the gate pins of the circuit breaker MOSFET pair. Once the LM5170-Q1 is enabled, an internal 330-µA current source starts to charge the circuit breaker MOSFET gates. The BRKG to BRKS voltage is internally clamped at 12 V.
35 CSB1 I CH-1 differential current sense inputs. The CSA1 pin connects to the CH-1 power inductor. The CSB1 pin connects to the circuit breaker, or directly to the LV-Port if the circuit breaker is not used. The CH-1 current sense resistor is placed between these two current sense pins. An internal 1-MΩ resistor is connected between the CSB1 and OVPB pins through an internal cutoff switch. During operation, the cutoff switch is closed and this internal resistor pulls up the OVPB pins. In shutdown mode, the internal resistor is disconnected by the cutoff switch.
36 CSA1 I
37 IOUT1 O CH-1 inductor current monitor pin. A current source proportional to the CH-1 inductor current flows out of this pin. Placing a terminating resistor and filter capacitor from IOUT1 to AGND produces a DC voltage representing the CH-1 DC current level. An internal 25-µA offset DC current source at the IOUT1 pin raises the active signal to be above the ground noise, thus improving the monitor noise immunity.
38 IOUT2 O CH-2 inductor current monitor pin. A current proportional to the CH-2 inductor current flows out of this pin. Placing a terminating resistor and filter capacitor from IOUT2 to AGND produces a DC voltage representing the CH-2 DC current level. An internal 25-µA offset DC current source at the IOUT2 pin raises the active signal above the ground noise, thus improving the monitor noise immunity.
39 EN1 I CH-1 enable pin. Pulling EN1 above 2.4 V turns off the SS pulldown and allows CH-1 to begin a soft-start sequence. Pulling EN1 below 1 V discharges the SS capacitor and holds it low. The high- and low-side gate drivers of both channels are held in the low state when SS is discharged.
40 SYNCIN I Input for an external clock that overrides the free-running internal oscillator. The SYNCIN pin can be left open or grounded when it is not used.
41 SYNCOUT O Clock output pin and fault check mode selector. SYNCOUT is connected to the downstream LM5170-Q1 in a 3- or 4-phase configuration. It also functions as a circuit breaker selection pin during start-up. Placing a 10-kΩ resistor from the SYNCOUT to AGND pins disables the fault check. feature. If no resistor is connected from SYNCOUT to AGND, the fault check is enabled.
42 ISETD I The PWM current programming pin. The inductor DC current level is proportional to the PWM duty cycle. Use either ISETA or ISETD but not both for channel current programming. When ISETD is not used, short ISETD to AGND.
43 EN2 I CH-2 enable pin. Pulling EN2 above 2.4 V enables CH-2. Pulling EN2 below 1 V shuts down the HO2 and LO2 drivers.
44 DIR I Direction command input. Pulling DIR above 2 V sets the converter to the buck mode, which commands the current to flow from the HV-Port to LV-Port. Pulling DIR below 1 V sets the converter to the boost mode, which commands the current to flow from the LV-Port to HV-Port. If the DIR pin is left open, the LM5170-Q1 detects an invalid command and disables both channels with the MOSFET gate drivers in the low state.
45 ISETA I, O The analog current programming pin. The inductor DC current is proportional to the ISETA voltage. Use either ISETA or ISETD but not both for channel current programming. When ISETA is not used, connect a 100-pF to 0.1-µF capacitor from ISETA to AGND.
46 AGND G Analog ground reference. AGND must connect to PGND externally through a single point connection to improve the LM5170-Q1 noise immunity.
47 OSC I The internal oscillator frequency is programmed by a resistor between OSC and AGND.
48 DT I A resistor connected between DT and AGND sets the dead time between the high-side and low-side driver outputs. Tie the DT pin to VCCA to activate the internal adaptive dead time control.
— EP — Exposed pad of the package. No internal electrical connections. Must be soldered to the large ground plane to reduce thermal resistance.
(1) Note: G = Ground, I = Input, O = Output, P = Power