SNVSBJ0B December 2019 – August 2021 LM5170
PRODUCTION DATA
The LM5170 can synchronize to an external clock if FEX_CLK is within ±20% of FOSC. The SYNCIN clock pulse width must be between 100 ns to 500 ns, with a high voltage level > 2 V and low voltage level < 1 V.
FEX_CLK can be adjusted dynamically. However, the LM5170 PLL takes approximately 500 µs to settle down to the newly asserted frequency. During the PLL transient, the instantaneous FSW can temporarily drop by 25%. To avoid overstress during the transient, TI recommends you reduce the load current to less than 50% by lowering the ISETA voltage or ISETD duty, or simply turn off the dual-channels by setting EN1 = EN2 = 0 when making an the external clock change.