SNVSBJ0A December   2019  – June 2020 LM5170

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Circuit
      2.      Channel Current Tracking ISETA Command
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Channel Current Setting Commands (ISETA or ISETD)

The LM5170 accepts the current setting command in the form of either an analog voltage or a PWM signal. The analog voltage uses the ISETA pin, and the PWM signal uses the ISETD pin. There is an internal ISETD decoder that converts the PWM duty ratio at the ISETD pin to an analog voltage at the ISETA pin. Owing to possible ground noise impact, TI recommends users to remove EN1 signal to achieve no load (0 A).

Figure 21 and Figure 22 show the pin configurations for current programming with an analog voltage or a PWM signal. The channel DC current is expressed in terms of resulted differential current sense voltage VCS_dc. When ISETA is used, the ISETD pin can be left open or connected to AGND. When ISETD is used, place a ceramic capacitor CISETA between the ISETA pin and AGND. CISETA and the internal 100-kΩ at the output of the ISETD decoder forms a low-pass RC filter to attenuate the ripple voltage on ISETA. However, the RC filter delays the ISETD dynamic change to be reflected on ISETA. To limit the delay not to exceed Tdelay_ISETD, the time constant of the RC filter should satisfy Equation 1.

Equation 1. LM5170 eq_1_SNVSAQ6.gif

Therefore, the maximum CISETA should be determined by Equation 2:

Equation 2. LM5170 eq_2_SNVSAQ6.gif

On the other hand, the time constant of the RC filter should be big enough for effective filtering. To attenuate the ripple by 40 dB, the RC filter corner frequency should be at least two decade below FISETD, that is, Equation 3

Equation 3. LM5170 eq_3_SNVSAQ6.gif

Therefore the minimum ISETD signal frequency should be determined by Equation 4:

Equation 4. LM5170 eq_4_SNVSAQ6.gif

For instance, if ISETA is required to settle down to the steady-state in 1 ms following an ISETD duty ratio step change, namely Tdelay_ISETD < 1 ms, the user should select CISETA < 2.5 nF, and FISETD > 64 kHz. If Tdelay_ISETD < 0.1 ms, then CISETA < 250 pF, and FISETD> 640 kHz. Note that the feedback loop property causes additional delay for the actual current to settle to the new regulation level.

LM5170 pin_configurations_for_current_setting_in_analog_voltage_signal_snvsbj0.gifFigure 21. Pin Configurations for Current Setting Using an Analog Voltage Signal
LM5170 pin_configurations_for_current_setting_in_pwm_signal_snvsbj0.gifFigure 22. Pin Configurations for Current Setting Using a PWM Signal

The ISETA pin is directly connected to the noninverting input of the error amplifier. By ISETA programming, the channel DC current is determined by Equation 5:

Equation 5. LM5170 eq_5_SNVSAQ6.gif

Or by Equation 6:

Equation 6. LM5170 eq_6_SNVSAQ6.gif

Or by Equation 7:

Equation 7. LM5170 eq_7_SNVSAQ6.gif

where

  • Rcs is the channel current sensing resistor value.

When using ISETD, the produced VISETA by the internal decoder is equal to the product of the effective duty ratio of the ISETD PWM signal (DISETD) and the 3.125-V internal reference voltage. The channel current is determined by Equation 8:

Equation 8. LM5170 eq_8_SNVSAQ6.gif

Or by Equation 9:

Equation 9. LM5170 eq_9_SNVSAQ6.gif

Or by Equation 10:

Equation 10. LM5170 eq_10_SNVSAQ6.gif