SNVSBJ0A December   2019  – June 2020 LM5170

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Circuit
      2.      Channel Current Tracking ISETA Command
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

FOSC = 100 kHz; VVCC = 10 V; VVIN = VHV-Port = 48 V and VLV-Port = 12 V, unless otherwise stated.(1)
PARAMETER TEST CONDITIONS MIN(3) TYP(2) MAX(3) UNIT
VIN SUPPLY (VIN, VINX)
ISHUTDOWN VIN pin current in shutdown mode VUVLO = 0 V 20 µA
ISTANDBY VIN pin current, no switching VVCC > 9 V, VUVLO > 2.5 V, VEN1 = VEN2 = 0 V 1 mA
VIN to VINX disconnect switch VUVLO < 1 V or VVCC < 7.5 V 5
VIN to VINX disconnect switch VUVLO > 2.6 V, VVCC > 9 V 100 Ω
VCC AND VCCA BIAS SUPPLIES
VCCUVLO VCC undervoltage detection VVCC falling 7.6 8 8.3 V
VCCHYS VCC UVLO hysteresis VVCC rising 8.1 8.5 8.9 V
IVCC_SD VCC sink current in shutdown mode VUVLO = 0 V 30 µA
IVCC_SB VCC sink current in standby: no switching VUVLO > 2.6 V, VEN1 = VEN2 = 0 V 10 mA
MASTER ON/OFF CONTROL (UVLO)
VUVLO_TH UVLO release threshold UVLO voltage rising 2.4 2.5 2.6 V
IHYS UVLO hysteresis current UVLO source current when VUVLO > 2.6 V 21 25 29 µA
VSD UVLO shutdown threshold (IC shutdown) UVLO voltage falling 1 1.25 1.5 V
UVLO shutdown release UVLO voltage rising above VSD 0.15 0.25 0.35 V
tUVLO UVLO glitch filter time UVLO voltage falling 2.5 µs
UVLO internal pulldown current 1 µA
CHANNEL ENABLE INPUTS EN1 AND EN2
VIL Enable input low state Disabled the driver outputs 1 V
VIH Enable input high state Enable the driver outputs 2 V
Internal pulldown impedance EN1, EN2 internal pulldown resistor 100 kΩ
EN glitch filter time (the rising and falling edges) 2 µs
DIRECTION COMMAND (DIR)
VDIR Command for current flowing from LV-Port to HV-Port (boost mode 12 V to 48 V) Actively pulled low by external circuit 1 V
Command for current flowing from HV-Port to LV-Port (buck mode 48 V to 12 V) Actively pulled high by external circuit 2 V
Standby (invalid DIR command) DIR neither active high nor active low 1.5 V
DIR glitch filter Both rising and falling edges 10 µs
ISET INPUT (ISETA, ISETD)
GISETA Regulated DC current sense voltage to ISETA voltage |VCSA – VCSB| = 50 mV 19.7 20 20.3 mV/V
ISETA internal pulldown resistor 170 kΩ
GISETD Conversion ratio of ISETA voltage to ISETD duty cycle ISETD frequency = 10 kHz, Duty = 100% 30.63 31.25 31.88 mV / %
VISETD _LO ISETD PWM signal low-state voltage 1 V
VISETD _HI ISETD PWM signal high-state voltage 2 V
ISETD internal pulldown resistor 100 kΩ
ISETD internal decoder filter resistor (tied to ISETA pin) 100 kΩ
OUTPUT CURRENT MONITOR (IOUT1, IOUT2)
GIOUT_BK1 IOUT1 and IOUT2 versus channel current sense voltage, in buck mode |VCSA – VCSB| = 50 mV, VDIR > 2 V 4.9 5 5.1 μA/mV
GIOUT_BST1 IOUT1 and IOUT2 versus channel current sense voltage, in boost mode |VCSA – VCSB| = 50 mV, VDIR < 1 V 4.9 5 5.1 μA/mV
GIOUT_BK2 IOUT1 and IOUT2 versus channel current sense voltage, in buck mode |VCSA – VCSB| = 10 mV, VDIR > 2 V, TJ = 25°C 4.91 5.18 5.43 μA/mV
GIOUT_BST2 IOUT1 and IOUT2 versus channel current sense voltage, in boost mode |VCSA – VCSB| = 10 mV, VDIR < 1 V, TJ = 25°C 4.47 4.77 5.1 μA/mV
IOUT1 and IOUT2 DC offset currents |VCSA – VCSB| = 0 mV 22 25 28 µA
CURRENT SENSE AMPLIFIER (BOTH CHANNELS)
GCS_BK1 Amplifier output to current sense voltage in buck mode |VCSA – VCSB| = 50 mV, VDIR > 2 V 49.25 50 50.75 V/V
GCS_BST1 Amplifier output to current sense voltage in boost mode |VCSA – VCSB| = 50 mV, VDIR < 1 V 49.25 50 50.75 V/V
GCS_BK2 Amplifier output to current sense voltage in buck mode |VCSA – VCSB| = 10 mV, VDIR > 2 V, TJ = 25°C 49 52 55 V/V
GCS_BST2 Amplifier output to current sense voltage in boost mode |VCSA – VCSB| = 10 mV, VDIR < 1 V, TJ = 25°C 45 48 51 V/V
BWCS Amplifier bandwidth 10 MHz
TRANSCONDUCTION AMPLIFIER (COMP1, COMP2)
Gm Transconductance 1 mA/V
ICOMP Output source current limit VISETA = 2.5 V, |VCSA – VCSB| = 10 mV 2 mA
Output sink current limit VISETA = 0 V, |VCSA – VCSB| = 50 mV –2 mA
BWgm Amplifier bandwidth 4 MHz
PWM COMPARATOR
COMP to output delay 50 ns
COMP to PWM offset 1 V
TOFF(min) Minimum OFF time 150 200 250 ns
RAMP GENERATOR (RAMP1 AND RAMP2)
RAMP discharge device RDS(on) 15 Ω
Threshold voltage for valid ramp signal 0.6 V
PEAK CURRENT LIMIT (IPK)
IPK internal current source 24.375 25 25.625 µA
IPKBuck Current sense voltage versus cycle-by-cycle limit threshold voltage given at IPK pin, in buck mode RIPK = 40 kΩ, VDIR > 2 V 35.8 46 58.9 mV/V
IPKBoost Current sense voltage versus cycle-by-cycle limit threshold voltage given at IPK pin, in boost mode RIPK = 40 kΩ, VDIR < 1 V 38.5 48 62.25 mV/V
OVERVOLTAGE PROTECTION (OVPA, OVPB)
OVP threshold OVP voltage rising 1.15 1.185 1.22 V
OVPHYS OVP hysteresis (falling edge) 100 mV
OVPA and OVPB glitch filter 5 µs
ROVPA Internal OVPA pullup resistor VINX to OVPA impedance 3
ROVPB Internal OVPB pullup resistor CSB1 to OVPB impedance, VUVLO > 2.6 V 1
OSCILLATOR (OSC)
Oscillator frequency 1 ROSC = 40 kΩ, SYNCIN open 90 100 110 kHz
Oscillator frequency 2 ROSC = 10 kΩ, SYNCIN open 335 375 410 kHz
VOSC OSC pin DC voltage 1.25 V
SYNCIN
VSYNIH SYNCIN input threshold for high state 2 V
VSYNIL SYNC SYNCIN input threshold for low state 1 V
Internal pulldown impedance VSYNCIN = 2.5 V 100 kΩ
Delay to establish synchronization 0.8 × FOSC < FSYNCIN < 1.2 × FOSC 200 µs
SYNCOUT
VSYNOH SYNCOUT high state 2.5 V
VSYNOL SYNCOUT low state 0.4 V
Sourcing current when SYNCOUT in high state VSYNCOUT = 2.5 V 1 mA
SYNCOUT pulse width 240 300 370 ns
SYNCOUT phase delay configurations VOPT > 2 V 90 Degree
VOPT < 1 V 120
RSYNCOUT Circuit breaker signature Use circuit breaker function and fault detection at start-up OPEN kΩ
Do not use circuit breaker function or disable fault detection at start-up 10
BOOTSTRAP (HB1, HB2)
VHB-UV Bootstrap undervoltage threshold (VHB – VSW) voltage rising 5.7 6.5 7.3 V
VHB-UV-HYS Hysteresis 0.5 V
IHB-LK Bootstrap quiescent current VHB – VSW = 10 V, VHO – VSW = 0 V 50 µA
HIGH-SIDE GATE DRIVERS (HO1, HO2)
VOLH HO low-state output voltage IHO = 100 mA 0.1 V
VOHH HO high-state output voltage IHO = –100 mA, VOHH = VHB – VHO 0.15 V
HO rise time (10% to 90% pulse magnitude) CLD = 1000 pF 5 ns
HO fall time (90% to 10% pulse magnitude) CLD = 1000 pF 4 ns
IOHH HO peak source current VHB – VSW = 10 V 4 A
IOLH HO peak sink current VHB – VSW = 10 V 5 A
LOW-SIDE GATE DRIVERS (LO1, LO2)
VOLL LO low-state output voltage ILO = 100 mA 0.1 V
VOHL LO high-state output voltage ILO = –100 mA, VOHL = VVCC – VLO 0.15 V
LO rise time (10% to 90% pulse magnitude) CLD = 1000 pF 5 ns
LO fall time (90% to 10% pulse magnitude) CLD = 1000 pF 4 ns
IOHL LO peak source current 4 A
IOLL LO peak sink current 5 A
INTERLEAVE PHASE DELAY FROM CH-2 To CH-1 (OPT)
VOPTL OPT input low state 1 V
VOPTH OPT input high state 2 V
HO2 on-time rising edge versus HO1 on-time rising edge, or LO2 on-time rising edge versus LO1 on-time rising edge VOPT > 2 V for 2, 4, 6, and 8 phases 175 180 185 Degrees
VOPT < 1 V for 3 phases 235 240 245
Internal pulldown impedance 1
DEAD TIME (DT)
tDT LO falling edge to HO rising edge delay RDT = 7.5 kΩ 40 ns
tDT HO falling edge to LO rising edge delay RDT = 7.5 kΩ 40 ns
VDT DC voltage level for programming 1.25 V
VDT DC voltage for adaptive dead time scheme only (short DT to VCCA) VCCA V
VADPT HO-SW or LO-GND voltage threshold to enable cross output for adaptive dead time scheme VVCC > 9 V, (VHB – VSW) > 8 V, HO or LO voltage falling 1.5 V
tADPT LO falling edge to HO rising edge delay VDT = VVCC 36 ns
tADPT HO falling edge to LO rising edge delay VDT = VVCC 41 ns
SOFT START (SS)
ISS SS charging current source VSS = 0 V 25 µA
VSS-OFFS SS to PWM comparator offset SS – PWM comparator noninverting input 1 V
RSS SS discharge device RDS(on) VSS = 2 V 30
VSS_LOW SS discharge completion threshold Once it is discharged by internal logic 0.23 V
DIODE EMULATION
Current zero cross threshold Current sense voltage 0 mV
CKT BREAKER CONTROL (BRKG, BRKS)
IBRKG Sourcing current nFAULT = 5 V, VVIN = 24 V, VBRKS = 12 V 275 330 375 µA
VBRK-CLP Voltage clamp nFAULT= 5 V, VVIN = 48 V, VBRKS = 12 V 9 14.5 V
RBRK-SINK Sinking capability nFAULT = 0 V 20
VREADY BRKG to BRKS voltage threshold to indicate readiness for operation Rising edge 6.5 8.5 V
IBRKG-LEAK BRKG leakage current nFAULT= 5 V, VVIN – VBRKS = 0 V,
VBRKG – VBRKS = 10 V
20 µA
FAULT ALARM (nFAULT)
In normal operation, no fault 4 5 V
Internal pull-up impedance for normal operation 30 kΩ
Internal pull-down FET RDS(on) after fault detected 125
External pull-down voltage threshold for IC shutdown 1 V
tFAULT External pul-ldown glitch filter 2 µs
td1_FAULT Delay time of nFAULT pull-down below 1 V to (VBRKG – VBRKS) < 1.5 V 5 µs
td2_FAULT Start-up fault detection duration VUVLO > 2.6 V, VVCC > 9 V 3 ms
THERMAL SHUTDOWN
TSD Thermal shutdown 175 ºC
TSD-HYS Thermal shutdown hysteresis 25 ºC
All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Typical values correspond to TJ = 25°C.
Minimum and maximum limits apply over the –40°C to 125°C junction temperature range.