SNVSBJ0A December 2019 – June 2020 LM5170
Each channel of the LM5170 has a robust 5-A (peak) half bridge driver to drive external N-channel power MOSFETs. As shown in Figure 26, the low-side drive is directly powered by VCC, and the high-side driver by the bootstrap capacitor CBT. During the on-time of the low-side driver, the SW pin is pulled down to PGND and CBT is charged by VCC through the boot diode DBT. TI recommends selecting a 0.1-µF or larger ceramic capacitor for CBT, and an ultra-fast diode of 1 A and 100-V ratings for DBT. TI also strongly recommends users to add a 2-Ω to 5-Ω resistor (RBT) in series with DBT to limit the surge charging current and improve the noise immunity of the high-side driver.
During start-up in buck mode, CBT may not be charged initially; the LM5170 then holds off the high-side driver outputs (HO1 and HO2) and sends LO pulses of 200-ns width in consecutive cycles to pre-charge CBT. When the boot voltage is greater than the 6.5-V boot UV threshold, the high-side drivers output PWM signals at the HO1 and HO2 pins for normal switching action.
During start-up in boost mode, CBT is naturally charged by the normal turnon of the low side MOSFET, therefore there is no such 200-ns pre-charge pulse at the LO pins.
To prevent shoot-through between the high-side and low-side power MOSFETs on the same half bridge leg, two types of dead time schemes can be chosen with the DT pin: the programmable dead time or built-in adaptive dead time.
To program the dead time, place a resistor RDT across the DT and AGND pins as shown in Figure 27.
Note that this equation is valid for programming tDT between 20 ns and 250 ns. When the power MOSFET is connected to the gate drive, its gate input capacitance CISS becomes a load of the gate drive output, and the HO and LO slew rate are reduced, leading to a reduced effective tDT between the high- and low-side MOSFETs. The user should evaluate the effective tDT to make sure it is adequate to prevent shoot-through between the high- and low-side MOSFETs.
When the DT programmability is not used, simply connect the DT pin to VCC as shown in Figure 29, to activate the built-in adaptive dead time. The adaptive dead time is implemented by real time monitoring of a driver’s output (either HO or LO) by the other driver (LO or HO) of the same half bridge switch leg, as shown in Figure 29 and Figure 30. Only when a driver’s output voltage falls below 1.25 V does the other driver starts turnon. The effectiveness of adaptive dead time is greatly reduced if a series gate resistor is used, or if the PCB traces of the gate drive have excessive impedance due to poor layout design.