SNVSBJ0A December   2019  – June 2020 LM5170

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application Circuit
      2.      Channel Current Tracking ISETA Command
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bias Supply (VCC, VCCA)
      2. 8.3.2  Undervoltage Lockout (UVLO) and Master Enable or Disable
      3. 8.3.3  High Voltage Input (VIN, VINX)
      4. 8.3.4  Current Sense Amplifier
      5. 8.3.5  Control Commands
        1. 8.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 8.3.5.2 Direction Command (DIR)
        3. 8.3.5.3 Channel Current Setting Commands (ISETA or ISETD)
      6. 8.3.6  Channel Current Monitor (IOUT1, IOUT2)
      7. 8.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 8.3.8  Error Amplifier
      9. 8.3.9  Ramp Generator
      10. 8.3.10 Soft Start
        1. 8.3.10.1 Soft-Start Control by the SS Pin
        2. 8.3.10.2 Soft Start by MCU Through the ISET Pin
        3. 8.3.10.3 The SS Pin as the Restart Timer
      11. 8.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT)
      12. 8.3.12 PWM Comparator
      13. 8.3.13 Oscillator (OSC)
      14. 8.3.14 Synchronization to an External Clock (SYNCIN, SYNCOUT)
      15. 8.3.15 Diode Emulation
      16. 8.3.16 Power MOSFET Failure Detection and Failure Protection (nFAULT, BRKG, BRKS)
        1. 8.3.16.1 Failure Detection Selection at the SYNCOUT Pin
        2. 8.3.16.2 Nominal Circuit Breaker Function
      17. 8.3.17 Overvoltage Protection (OVPA, OVPB)
        1. 8.3.17.1 HV-V- Port OVP (OVPA)
        2. 8.3.17.2 LV-Port OVP (OVPB)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Multiphase Configurations (SYNCOUT, OPT)
        1. 8.4.1.1 Multiphase in Star Configuration
        2. 8.4.1.2 Configuration of 2, 3, or 4 Phases in Master-Slave Daisy-Chain Configurations
        3. 8.4.1.3 Configuration of 6 or 8 Phases in Master-Slave Daisy-Chain Configurations
      2. 8.4.2 Multiphase Total Current Monitoring
    5. 8.5 Programming
      1. 8.5.1 Dynamic Dead Time Adjustment
      2. 8.5.2 Optional UVLO Programming
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Key Waveforms
        1. 9.1.1.1 Typical Power-Up Sequence
        2. 9.1.1.2 One to Eight Phase Programming
      2. 9.1.2 Inner Current Loop Small Signal Models
        1. 9.1.2.1 Small Signal Model
        2. 9.1.2.2 Inner Current Loop Compensation
      3. 9.1.3 Compensating for the Non-Ideal Current Sense Resistor
      4. 9.1.4 Outer Voltage Loop Control
    2. 9.2 Typical Application
      1. 9.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Determining the Duty Cycle
          2. 9.2.1.2.2  Oscillator Programming
          3. 9.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 9.2.1.2.4  Current Sense (RCS)
          5. 9.2.1.2.5  Current Setting Limits (ISETA or ISETD)
          6. 9.2.1.2.6  Peak Current Limit
          7. 9.2.1.2.7  Power MOSFETS
          8. 9.2.1.2.8  Bias Supply
          9. 9.2.1.2.9  Boot Strap
          10. 9.2.1.2.10 RAMP Generators
          11. 9.2.1.2.11 OVP
          12. 9.2.1.2.12 Dead Time
          13. 9.2.1.2.13 IOUT Monitors
          14. 9.2.1.2.14 UVLO Pin Usage
          15. 9.2.1.2.15 VIN Pin Configuration
          16. 9.2.1.2.16 Loop Compensation
          17. 9.2.1.2.17 Soft Start
          18. 9.2.1.2.18 ISET Pins
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

The LM5170 device is a high performance, dual-channel bidirectional current controller intended to manage current transfer between a Higher Voltage Port (HV-Port) and a Lower Voltage Port (LV-Port). It integrates essential analog functions that enable the design of high power converters with a minimal number of external components. It regulates DC current in the direction designated by the DIR pin input signal. The current regulation level is programmed by the analog signal applied at the ISETA pin or the digital PWM signal at the ISETD pin. Independent enable signals activate each channel of the dual controller.

The dual-channel differential current sense amplifiers and dedicated channel current monitors achieve typical accuracy of 1%. The robust 5-A half-bridge gate drivers are capable of controlling parallel MOSFET switches delivering 500 W or more per channel. The diode emulation mode of the buck or boost synchronous rectifiers enables discontinuous mode operation for improved efficiency under light load conditions, and it also prevents negative current. Versatile protection features include the cycle-by-cycle peak current limit, overvoltage protection of both 48-V and 12-V battery rails, detection and protection of MOSFET switch failures, and overtemperature protection.

The LM5170 uses average current mode control which simplifies compensation by eliminating the right-half plane zero in the boost operating mode and by maintaining a constant loop gain regardless of the operating voltages and load level. The free-running oscillator is adjustable up to 500 kHz and can be synchronized to an external clock within ±20% of the free running oscillator frequency. Stackable multiphase parallel operation is achieved by connecting two LM5170 controllers in parallel for 3 or 4 phase operation, or by synchronizing multiple LM5170 controllers to external multiphase clocks for a higher number of phases. The UVLO pin provides master ON/OFF control that disables the LM5170 in a low quiescent current shutdown state when the pin is held low.

Definition of IC Operation Modes:

  • Shutdown Mode: When the UVLO pin is < 1.25 V, or VCC < 8 V, or nFAULT < 1.25 V, the LM5170 is in the shutdown mode with all gate drivers in the low state, all internal logic reset, and the VINX pin disconnected from the VIN pin. When UVLO < 1.25 V, the IC draws < 20 µA through the VIN and VCC pins.
  • Initialization Mode: When the UVLO pin is > 1.5 V but < 2.5 V, and VCC > 8.5 V, and nFAULT > 2 V, the LM5170 establishes proper internal logic states and prepares for circuit operation.
  • Standby Mode: When the UVLO pin is > 2.5 V, and VCC > 8.5 V, and nFAULT > 2 V, the LM5170 first performs fault detection for 2 to 3 ms, during which the external power MOSFETs are each checked for drain-to-source short-circuit conditions. If a fault is detected, the LM5170 returns to the shutdown mode and is latched in shutdown until reset through UVLO or VCC pins. If no failure is detected, the LM5170 is ready to operate. The circuit breaker MOSFETs are turned on and the oscillator and ramp generators are activated, but the four gate drive outputs remain off until the EN1 or EN2 initiate the power delivery mode.
  • Power Delivery Mode: When the UVLO pin > 2.5 V, VCC > 8.5 V, nFAULT > 2 V, EN1 or EN2 > 2 V, DIR is valid ( > 2 V or < 1 V), and ISETA > 0 V, the SS capacitor is released and the LM5170 regulates the DC current at the level set at the ISETA pin.