SNVSAA7B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Components Selection
            1. Input Capacitors
              1. Input Capacitor Selection
            2. Output Inductors and Capacitors Selection
              1. Inductor Selection
              2. Output Capacitor Selection
          2. Setting the Output Voltage
            1. FB for Adjustable Versions
          3. VCC
          4. BIAS
          5. CBOOT
          6. Maximum Ambient Temperature
        3. Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 Adjustable Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNL|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Design Procedure

  • BIAS is connected to the output. This example assumes that the load is close to the output so no bias resistance is necessary. A 0.1-µF capacitor is still recommended close to the bias pin.
  • FB is connected directly to the output. BIAS and FB are connected to the output via separate traces. This is important to reduce noise and achieve good performances. See Section 11.1 for more details on the proper layout method.
  • SYNC is connected to ground directly as there is no need for this function in this application.
  • EN is connected to VIN so the device perates as soon as the input voltage rises above the VIN-OPERATE threshold.
  • FPWM is connected to GND. This causes the device to operate in AUTO mode. In this mode, the switching frequency is adjusted at light loads to keep efficiency maximum. As a result the switching frequency will change with the output current until medium load is reached. The part will then switch at the frequency defined by FSW. See Section 8.4 for more details.
  • A 4.7-µF capacitor is connected between VCC and GND close to the VCC pin This ensures stable operation of the internal LDO.
  • RESET is biased to an external rail in this example. A pullup resistor is necessary. A 100 kΩ is selected for this application and is generally sufficient. The value can be selected to match the needs of the application but must not lead to excessive current into the RESET pin when RESET is in a low state. Consult Section 7.1 for the maximum current allowed. In addition, a low pull-up resistor could lead to an incorrect logic level due to the value of RRESET . Consult Section 7.5 for details on the RESET pin.
  • it is important to connect small high frequency capacitors CIN_HF1 and CIN_HF2 as close to both inputs PVIN1 and PVIN2 as possible. For the detailed process of choosing input capacitors, refer to Section
  • Output capacitor selection is detailed in Section
  • Inductor selection is detailed in Section In general, a 2.2-µH inductor is recommended for the fixed output options. For the adjustable options, the inductance can vary with the output voltage due to ripple and current limit requirements.