SNVSAA7B December   2015  – July 2021 LM53625-Q1 , LM53635-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Timing Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 Control Scheme
    3. 8.3 Feature Description
      1. 8.3.1 RESET Flag Output
      2. 8.3.2 Enable and Start-Up
      3. 8.3.3 Soft-Start Function
      4. 8.3.4 Current Limit
      5. 8.3.5 Hiccup Mode
      6. 8.3.6 Synchronizing Input
      7. 8.3.7 Undervoltage Lockout (UVLO) and Thermal Shutdown (TSD)
      8. 8.3.8 Input Supply Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 AUTO Mode
      2. 8.4.2 FPWM Mode
      3. 8.4.3 Dropout
      4. 8.4.4 Input Voltage Frequency Foldback
    5. 8.5 Spread-Spectrum Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 General Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Components Selection
            1. Input Capacitors
              1. Input Capacitor Selection
            2. Output Inductors and Capacitors Selection
              1. Inductor Selection
              2. Output Capacitor Selection
          2. Setting the Output Voltage
            1. FB for Adjustable Versions
          3. VCC
          4. BIAS
          5. CBOOT
          6. Maximum Ambient Temperature
        3. Application Curves
      2. 9.2.2 Fixed 5-V Output for USB-Type Applications
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 9.2.3 Fixed 3.3-V Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 9.2.4 Adjustable Output
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNL|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Control Scheme

The LM53625/35-Q1 control scheme allows this device to operate under a wide range of conditions with a low number of external components. Peak current mode control allows a wide range of input voltages and output capacitance values, while maintaining a constant switching frequency. Stable operation is maintained while output capacitance is changed during operation as well. This allows use in systems that require high performance during load transients and which have load switches that remove loads as system operating state changes. Short minimum on and off times ensure constant frequency regulation over a wide range of conversion ratios. These on and off times allow for a duty factor window of 13% to 87% at 2.1-MHz switching frequency.

This architecture uses frequency spreading in order to achieve low dropout voltage maintaining output regulation as the input voltage falls close to output voltage. The frequency spreading is smooth and continuous, and activated as off time approaches its minimum. Under these conditions, the LM53625/35-Q1 operates much like a constant off-time converter allowing the maximum duty cycle to reach 98% and output voltage regulation with 300-mV dropout at 3.5 A.

While input voltage is high enough to require duty factor below 13%, frequency is reduced smoothly to allow lower duty factors. In this mode many of the beneficial properties of current-mode control such as insensitivity to output capacitance is maintained. The LM53625/35-Q1 has short enough minimum on time to maintain 2.1-MHz operation while converting a 18 V input to a 3.3-V output.

As load current is reduced, the LM53625/35-Q1 transitions to light load mode. In this mode, diode emulation is used to reduce RMS inductor current and switching frequency is reduced. Also, fixed voltage versions do not need a voltage divider connected to FB saving additional power. As a result, only 15 µA (typical, while converting 13.5 V to 3.3 V) is consumed to regulate output voltage if output is unloaded. Average output voltage increases slightly while lightly loaded as well.

For applications that require constant operating frequency regardless of the load condition, the FPWM pin allows the user to disable the light load operating mode. The device then switches at 2.1 MHz regardless of the output current. Diode emulation is also turned off when the FPWM pin is set high.