SNVSBY6 October 2021 LM61430-Q1
The PGOOD function is implemented to replace a discrete reset device, reducing BOM count and cost. The PGOOD pin voltage goes low when the feedback voltage is outside of the specified PGOOD thresholds (see Figure 7-7). This can occur in current limit and thermal shutdown, as well as while disabled and during normal start-up. A glitch filter prevents false flag operation for short excursions of the output voltage, such as during line and load transients. Output voltage excursions that are shorter than tPGDFLT_FALL do not trip the power-good flag. Power-good operation can be best understood by referring to Figure 8-6.
The power-good output consists of an open-drain NMOS; requiring an external pullup resistor to a suitable logic supply or VOUT. When EN is pulled low, the flag output is also forced low. With EN low, power good remains valid as long as the input voltage is ≥ 1 V (typical).
|FAULT CONDITION INITIATED||FAULT CONDITION ENDS (AFTER WHICH tPGDFLT(rise) MUST PASS BEFORE PGOOD OUTPUT IS RELEASED)(1)|
|VOUT < VOUT-target × PGDUV AND t > tPGDFLT(fall)||Output voltage in regulation: |
VOUT-target × (PGDUV + PGDHYST) < VOUT < VOUT-target × (PGDOV - PGDHYST) (See Figure 7-7.)
|VOUT > VOUT-target × PGDOV AND t > tPGDFLT(fall)||Output voltage in regulation|
|TJ > TSD_R||TJ < TSD_F AND output voltage in regulation|
|EN < VEN falling||EN > VEN Rising AND output voltage in regulation|
|VCC < VCC_UVLO - VCC_UVLO_HYST||VCC > VCC_UVLO AND output voltage in regulation|