SNVSB55G February   2019  – September 2022 LM63615-Q1 , LM63625-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1.     Absolute Maximum Ratings
    2. 7.1 ESD Ratings
    3. 7.2 Recommended Operating Conditions
    4. 7.3 Thermal Information
    5. 7.4 Electrical Characteristics
    6. 7.5 Timing Characteristics
    7. 7.6 Switching Characteristics
    8. 7.7 System Characteristics
    9. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sync/Mode Selection
      2. 8.3.2 Output Voltage Selection
      3. 8.3.3 Switching Frequency Selection
        1. 8.3.3.1 Spread Spectrum Option
      4. 8.3.4 Enable and Start-up
      5. 8.3.5 RESET Flag Output
      6. 8.3.6 Undervoltage Lockout and Thermal Shutdown and Output Discharge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Light Load Operation
        1. 8.4.2.1 Sync/FPWM Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Minimum On-time Operation
      5. 8.4.5 Current Limit and Short-Circuit Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 CFF Selection
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Full Feature Design Example
      4. 9.2.4 Application Curves
      5. 9.2.5 EMI Performance Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Glossary
    7. 12.7 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.1.1 Ground and Thermal Considerations

As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the AGND and PGND pins to the ground planes using vias next to the bypass capacitors. PGND pins are connected directly to the source of the low-side MOSFET switch and also connected directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching frequency and can bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be constrained to one side of the ground planes. The other side of the ground plane contains much less noise and must be used for sensitive routes.

TI recommends providing adequate device heat sinking by using the thermal pad (DAP) of the device as the primary thermal path. Use a minimum 4 × 3 array of 10 mil thermal vias to connect the DAP to the system ground plane heat sink. The vias must be evenly distributed under the DAP. Use as much copper as possible for system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with enough copper thickness and proper layout provides low current conduction impedance, proper shielding, and lower thermal resistance.