SNVSBK9C November   2019  – September 2020 LM63635-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Sync/Mode Selection
      2. 8.3.2 Output Voltage Selection
      3. 8.3.3 Switching Frequency Selection
        1. 8.3.3.1 Spread Spectrum Option
      4. 8.3.4 Enable and Start-up
      5. 8.3.5 RESET Flag Output
      6. 8.3.6 Undervoltage Lockout and Thermal Shutdown and Output Discharge
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Light Load Operation
        1. 8.4.2.1 Sync/FPWM Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Minimum On-time Operation
      5. 8.4.5 Current Limit and Short-Circuit Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Choosing the Switching Frequency
        2. 9.2.2.2 Setting the Output Voltage
          1. 9.2.2.2.1 CFF Selection
        3. 9.2.2.3 Inductor Selection
        4. 9.2.2.4 Output Capacitor Selection
        5. 9.2.2.5 Input Capacitor Selection
        6. 9.2.2.6 CBOOT
        7. 9.2.2.7 VCC
        8. 9.2.2.8 External UVLO
        9. 9.2.2.9 Maximum Ambient Temperature
      3. 9.2.3 Full Feature Design Example
      4. 9.2.4 Application Curves
      5. 9.2.5 EMI Performance Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground and Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Glossary
    6. 12.6 Electrostatic Discharge Caution
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore, the EMI performance of the regulator is dependent on the PCB layout to a great extent. In a buck converter, the most critical PCB feature is the loop formed by the input capacitors and power ground, as shown in Figure 11-1. This loop carries large transient currents that can cause large transient voltages when reacting with the trace inductance. These unwanted transient voltages disrupt the proper operation of the converter. Because of this, the traces in this loop must be wide and short, and the loop area as small as possible to reduce the parasitic inductance. Figure 11-2 and Figure 11-3 show recommended layouts for the critical components of the LM63635-Q1.

  1. Place the input capacitors as close as possible to the VIN and PGND terminals. VIN and PGND pins are adjacent, simplifying the input capacitor placement. Thermal reliefs in this area are not recommended.
  2. Place a bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device and routed with short, wide traces to the VCC and PGND pins. Thermal reliefs in this area are not recommended.
  3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short and wide traces to the BOOT and SW pins. Thermal reliefs in this area are not recommended.
  4. Place the feedback divider as close as possible to the FB pin of the device. If an external feedback divider is used with the ADJ option, place RFBB, RFBT, and CFF close to the device. The connections to FB and AGND must be short and close to those pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of the regulator.
  5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act as a heat dissipation path.
  6. Connect the thermal pad to the ground plane. The thermal pad (DAP) connection must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an electrical ground connection for the regulator. The integrity of this solder connection has a direct bearing on the total effective RθJA of the application. Thermal reliefs in this area are not recommended.
  7. Provide wide paths for VIN, VOUT, SW, and PGND. Making these paths as wide and direct as possible reduces any voltage drops on the input or output paths of the converter and maximizes efficiency. Thermal reliefs in this area are not recommended.
  8. Provide enough PCB area for proper heat-sinking. As stated in Section 9.2.2.9, enough copper area must be used to ensure a low RθJA, commensurate with the maximum load current and ambient temperature. The top and bottom PCB layers must be made with two-ounce copper and no less than one ounce. Use an array of heat-sinking vias to connect the thermal pad (DAP) to the ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended), these thermal vias can also be connected to the inner layer heat-spreading ground planes.
  9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as possible. At the same time, the total area of this node must be minimized to help reduce radiated EMI.

See the following PCB layout resources for additional important guidelines:

GUID-DDA21A08-3FC6-450F-B00C-2CE3359FCC63-low.gifFigure 11-1 Current Loops With Fast Edges