SNVSBK9C November   2019  – September 2020

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Device Comparison Table
6. Pin Configuration and Functions
7. Specifications
8. Detailed Description
1. 8.1 Overview
2. 8.2 Functional Block Diagram
3. 8.3 Feature Description
4. 8.4 Device Functional Modes
9. Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
1. 9.2.1 Design Requirements
2. 9.2.2 Detailed Design Procedure
3. 9.2.3 Full Feature Design Example
4. 9.2.4 Application Curves
5. 9.2.5 EMI Performance Curves
3. 9.3 What to Do and What Not to Do
10. 10Power Supply Recommendations
11. 11Layout
1. 11.1 Layout Guidelines
2. 11.2 Layout Example
12. 12Device and Documentation Support
13. 13Mechanical, Packaging, and Orderable Information

• PWP|16
• DRR|12
• PWP|16
• DRR|12

#### 9.2.2.4 Output Capacitor Selection

The value of the output capacitor and its ESR determine the output voltage ripple and load transient performance. The output capacitor bank is usually limited by the load transient requirements rather than the output voltage ripple. Use Equation 9 to estimate a lower bound on the total output capacitance, and an upper bound on the ESR, which are required to meet a specified load transient.

Equation 9.

where

• ΔVOUT = output voltage transient
• ΔIOUT = output current transient
• K = ripple factor from Section 9.2.2.3

Once the output capacitor and ESR have been calculated, use Equation 10 to check the peak-to-peak output voltage ripple, Vr.

Equation 10.

The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple requirements.

This example requires a ΔVOUT of ≤ 200 mV for an output current step of ΔIOUT = 3.25 A. Equation 9 gives a minimum value of 28 µF and a maximum ESR of 0.056 Ω. Assuming a 20% tolerance and a 10% bias de-rating, the user arrives at a minimum capacitance of 39 µF. This can be achieved with a bank of 2 × 22-µF, 16-V, ceramic capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response. Ceramic capacitors can easily meet the minimum ESR requirements. In some cases, an aluminum electrolytic capacitor can be placed in parallel with the ceramics to build up the required value of capacitance. When using a mixture of aluminum and ceramic capacitors, use the minimum recommended value of ceramics and add aluminum electrolytic capacitors as needed.

In general, use a capacitor rating of at least 10 V for output voltages of 3.3 V or less, and use a capacitor of 16 V or more for output voltages of 5 V and above.

The recommendations given in Table 9-1 provide typical and minimum values of output capacitance for the given conditions. These values are the rated or nameplate figures. If the minimum values are to be used, the design must be tested over all of the expected application conditions, including input voltage, output current, and ambient temperature. This testing must include both bode plot and load transient assessments. The maximum value of total output capacitance must be limited to about 10 times the design value, or 1000 µF, whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of start-up at full load and loop stability must be performed.

In practice, the output capacitor has the most influence on the transient response and loop phase margin. Load transient testing and bode plots are the best way to validate any given design and must always be completed before the application goes into production. In addition to the required output capacitance, a small ceramic placed on the output can reduce high frequency noise. Small case size ceramic capacitors in the range of 1 nF to 100 nF can help reduce spikes on the output caused by inductor and board parasitics.