SNVSCF0 October   2024 LM65680-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  EN Pin and Use as VIN UVLO
      3. 7.3.3  Device Configuration
      4. 7.3.4  Single-Output Dual-Phase Operation
      5. 7.3.5  Mode Selection
        1. 7.3.5.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.5.2 Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage (BST Pin)
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Safety Features
        1. 7.3.11.1 Power-Good Monitor
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup
        4. 7.3.11.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Feed-forward Capacitor (CFF)
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Choosing the Switching Frequency
        6. 8.2.2.6 Setting the Output Voltage
        7. 8.2.2.7 Compensation Components
        8. 8.2.2.8 CBST
        9. 8.2.2.9 External UVLO
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 RZY 26-Pin WQFN-FCRLF Package (Top View)
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
NC1ANo connect pin. Leave floating.
PG2OPower-Good output pin. This pin is an open-collector output that goes low if the output voltage is outside of the specified regulation window.
COMP3AExternal compensation pin. This pin is the output of the transconductance amplifier. If used, connect a compensation network from the COMP pin to PGND. If unused, the pin must be tied to VCC.
FB4AFeedback pin. Connect to GND to configure 3.3V fixed output voltage. Connect to VCC to configure 5V fixed output voltage. Connect this pin to a feedback divider tap point for adjustable output options. The regulation threshold is 0.8V.
SS5ASoft-start delay programming pin. If the SS pin is left open, the internal soft-start circuit ramps the FB reference from zero to full value in 5.3ms. If a capacitor is connected from the SS pin to PGND, the soft-start time can be set to a higher value.
SGND6G Sense GND pin. Connect to the system ground.
CONFIG / CLKOUT7I/OConfiguration pin. This pin configures the device as a primary (1-phase or 2-phase operation) or a secondary (2-phase operation) and selects internal (1-phase operation) or external compensation (1-phase or 2-phase operation). If configured as a primary for 2-phase operation, the pin becomes a CLKOUT pin after start-up.
MODE / SYNC8I/OMode and synchronization input pin. Tie this pin to PGND or drive the pin low to operate in AUTO mode. Tie this pin to VCC or drive the pin high, or send a synchronization clock signal to operate in FPWM mode. When synchronized to an external clock, use the RT pin to set the internal frequency close to the synchronized frequency to avoid disturbances if the external clock is turned on and off.
RT9I/OSwitching frequency programming pin. Connect this pin to PGND through a resistor with a value between 6.81kΩ and 54.2kΩ to set the switching frequency between 300kHz and 2200kHz. Connect to VCC for 400kHz operation. Connect to PGND for 2.2MHz operation. Do not float.
EN / UVLO10PPrecision enable pin. Drive this pin high / low to enable / disable the device. This pin can be directly connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. Do not float.
NC11ONo connect pin. Leave floating.
PGND112GPower ground to the internal low-side MOSFET. Connect this pin to the system ground. Low-impedance connection must be provided to PGND2. Connect a high-quality bypass capacitor or capacitors from this pin to VIN1.
NC13—No connect pin. Leave floating to maintain 1mm clearance between PGND1 and VIN1 pins. This pin be shorted to PGND1 provided the 0.75mm clearance between PGND1 and VIN1 pins meets system pin clearance requirements.
VIN114PInput supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this pin to PGND1. Provide a low-impedance connection to VIN2.
NC15—No connect pin. Leave floating to maintain 0.5mm clearance between VIN1 and SW1.
SW116PDevice switch pins and the switch node of the regulator. Connect to the output inductor.
SW217P
SW318P
BST19PHigh-side driver upper supply rail. Connect a 100nF capacitor between the SW node and BST. An internal diode charges the capacitor while SW node is low.
NC20—No connect pin. Leave floating to maintain 0.5mm clearance between VIN2 and BST.
VIN221PInput supply to the regulator. Connect a high-quality bypass capacitor or capacitors from this pin to PGND2. Provide a low-impedance connection to VIN1.
NC22—No connect pin. Leave floating to maintain 1mm clearance between PGND2 and VIN2 pins. This pin be shorted to PGND2 provided the 0.75mm clearance between PGND2 and VIN2 pins meets system pin clearance requirements.
PGND223GPower ground to internal low-side MOSFET. Connect to system ground. Low-impedance connection must be provided to PGND1. Connect a high-quality bypass capacitor or capacitors from this pin to VIN2.
VCC24PInternal regulator output. Used as supply to internal control circuits. Do not connect this pin to any external loads. Connect a high-quality 1µF capacitor from this pin to PGND.
DRSS / MODECOMM25I/ODual Random Spread-Spectrum (DRSS) select pin. See Dual Random Spread Spectrum (DRSS) for available DRSS options. If configured for 2-phase operation, this pin becomes a mode communication pin between a primary and a secondary device. For 2-phase operation, tie together the MODECOMM pins of the primary and secondary devices.
BIAS26PInput to internal voltage regulator. If configured for fixed VOUT, connect the pin to the VOUT node to close the control loop. If configured for an adjustable VOUT, connect the pin to the VOUT node or an external bias supply from 3.3V to 30V. If output voltage is above 30V and no external supply is used, tie the pin to GND.
PGND27GExposed PGND pad. Connect to system GND on a PCB. This pin is a major heat dissipation path for the die. The pad must be used for heat sinking by soldering to a large copper area on a PCB. Implementing as many thermal vias as suggested in the example board layout makes sure of lowest package thermal resistance and best possible thermal performance.
(1) I = input, O = output, A = analog, G = ground, P = power