SNVSCF0 October   2024 LM65680-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Output Voltage Selection
      2. 7.3.2  EN Pin and Use as VIN UVLO
      3. 7.3.3  Device Configuration
      4. 7.3.4  Single-Output Dual-Phase Operation
      5. 7.3.5  Mode Selection
        1. 7.3.5.1 MODE/SYNC Pin Uses for Synchronization
        2. 7.3.5.2 Clock Locking
      6. 7.3.6  Adjustable Switching Frequency
      7. 7.3.7  Dual Random Spread Spectrum (DRSS)
      8. 7.3.8  Internal LDO, VCC UVLO, and BIAS Input
      9. 7.3.9  Bootstrap Voltage (BST Pin)
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Safety Features
        1. 7.3.11.1 Power-Good Monitor
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup
        4. 7.3.11.4 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Train Components
        1. 8.1.1.1 Buck Inductor
        2. 8.1.1.2 Output Capacitors
        3. 8.1.1.3 Input Capacitors
        4. 8.1.1.4 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
      3. 8.1.3 Maximum Ambient Temperature
        1. 8.1.3.1 Derating Curves
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Feed-forward Capacitor (CFF)
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Choosing the Switching Frequency
        6. 8.2.2.6 Setting the Output Voltage
        7. 8.2.2.7 Compensation Components
        8. 8.2.2.8 CBST
        9. 8.2.2.9 External UVLO
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.3 Feed-forward Capacitor (CFF)

The value of the CFF capacitor is calculated so that the resulting phase margin of the overall system is improved. The addition of the CFF capacitor does not change the response of the system at the DC level or at lower frequencies. At higher frequencies, the capacitor helps reduce the impedance from VOUT to FB. This action helps propagate any high frequency change due to a fast load transient at the output to the feedback, and allows the error amplifier to correct for this.

In the frequency domain, the addition of the CFF capacitor creates an additional zero and a pole. The zero is caused by the interaction of CFF with the upper feedback resistor RFBT. This action helps increase the gain by 20dB/decade and gives the necessary phase boost. The zero frequency is given in Equation 39:

Equation 31. f Z = 1 2   ×   π   ×   R F B T   ×   C F F

The pole is caused by the interaction of CFF with the parallel combination of the upper feedback resistors RFBT and the lower feedback resistor RFBB. The pole decreases the gain by 20dB/dec, and helps to roll off the gain after the system crossover. Gain margin is also increased. The pole frequency is given in Equation 32:

Equation 32. f P = 1 2   ×   π   ×   ( R F B T   ||   R F B B )   ×   C F F

From Equation 39 and Equation 32, if the CFF increases, the zero moves to lower frequencies. The pole also moves to lower frequencies, and if the value of CFF is not optimized, the actions of the zero and the pole nearly cancel each other out. This event is exacerbated at relatively lower outputs, where the pole and zero frequencies are very close. To obtain the best performance from the CFF capacitor, the value of CFF must be optimized.

The CFF capacitor optimization relies on the idea that if the zero and pole frequencies are aligned so that the system crossover frequency without the use of CFF (fNO_CFF) is exactly between the pole and zero frequencies caused by the CFF, then the most optimum phase boost is obtained at the crossover frequency. The CFF pole follows after the crossover frequency and assists the gain roll off for better gain margin. The equation is as follows:

Equation 33. f N O _ C F F   =     f Z × f P

Substituting Equation 39 and Equation 32 into Equation 33 results in Equation 34, which is now a function of RFBT, RFBB, and fNO_CFF.

Equation 34. C F F _ O P T   =     R F B T   +   R F B B 2   ×   π   ×   f N O _ C F F   ×   R F B T   ×     R F B B

Where,

  • CFF_OPT = optimized feed-forward capacitor
  • RFBT = upper feedback resistor
  • RFBB = lower feedback resistor
  • fNO_CFF = system crossover frequency without the use of CFF