SNOSDC0A October   2020  – December 2020 LM7310


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Reverse Polarity Protection
      2. 7.3.2 Undervoltage Protection (UVLO & UVP)
      3. 7.3.3 Overvoltage Lockout (OVLO)
      4. 7.3.4 Inrush Current control and Fast-trip
        1. Slew Rate (dVdt) and Inrush Current Control
        2. Fast-Trip During Steady State
      5. 7.3.5 Analog Load Current Monitor Output
      6. 7.3.6 Reverse Current Protection
      7. 7.3.7 Overtemperature Protection (OTP)
      8. 7.3.8 Fault Response
      9. 7.3.9 Power Good Indication (PG)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
      1. 8.2.1 Typical Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Setting Undervoltage and Overvoltage Thresholds
          2. Setting Output Voltage Rise Time (tR)
          3. Setting Power Good Assertion Threshold
          4. Setting Analog Current Monitor Voltage (IMON) Range
        3. Application Curves
    3. 8.3 Active ORing
    4. 8.4 Priority Power MUXing
    5. 8.5 USB PD Port Protection
    6. 8.6 Parallel Operation
  9. Power Supply Recommendations
    1. 9.1 Transient Protection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Active ORing

A typical redundant power supply configuration is shown in Figure 8-7 below. Schottky ORing diodes have been popular for connecting parallel power supplies, such as parallel operation of wall adapter with a battery or a hold-up storage capacitor. Similar ORing requirements can be seen in end equipements such as PC, Notebook, Docking stations, Monitors etc.. which can take power from multiple USB ports and/or power adapter. The disadvantage of using ORing diodes is high voltage drop and associated power loss. The LM73100 with integrated, low-ohmic, back-to-back FETs provides a simple and efficient solution. Figure below shows the Active ORing implementation using the devices.

GUID-20201214-CA0I-PWZF-N9CB-H4KLVPQBFSZS-low.gifFigure 8-7 Two Devices, Active ORing Configuration

The linear ORing mechanism in LM73100 ensures that there's no reverse current flowing from one power source to the other during fast or slow ramp of either supply.

The following waveforms illustrate the active ORing behavior.

VIN1 = 12 V, ROUT = 25 Ω, COUT = 440 μF, IN2 stepped up to 13 V and then ramped down
Figure 8-8 Active ORing Response
VIN1 = 12 V, ROUT = 25 Ω, COUT = 440 μF, IN2 stepped up to 13 V and then ramped down
Figure 8-9 Active ORing Response

When bus voltages (IN1 and IN2) are matched, device in each rail sees a forward voltage drop and is ON delivering the load current. During this period, current is shared between the rails in the ratio of differential voltage drop across each device.

In addition to supply ORing, the devices protect the system from overvoltage, excessive inrush current and transient overcurrent events during steady state.


  1. ORing can be done either between two similar rails (such as 12 V & 12 V; 3.3 V & 3.3 V) or between dissimilar rails (such as 12 V & 5 V).
  2. For ORing cases with skewed voltage combinations, care must be taken to design circuit components on PGTH, EN/UVLO & OVLO pins for the lower voltage channel device such that the absolute maximum ratings on those pins are not exceeded when higher voltage is present on the other channel. Also, the dVdt pin capacitor rating should be chosen based on the highest of the 2 supplies. Refer to Absolute Maximum Ratings and Recommended Operating Conditions tables for more details.