SNOSDC0A October   2020  – December 2020 LM7310


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Reverse Polarity Protection
      2. 7.3.2 Undervoltage Protection (UVLO & UVP)
      3. 7.3.3 Overvoltage Lockout (OVLO)
      4. 7.3.4 Inrush Current control and Fast-trip
        1. Slew Rate (dVdt) and Inrush Current Control
        2. Fast-Trip During Steady State
      5. 7.3.5 Analog Load Current Monitor Output
      6. 7.3.6 Reverse Current Protection
      7. 7.3.7 Overtemperature Protection (OTP)
      8. 7.3.8 Fault Response
      9. 7.3.9 Power Good Indication (PG)
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
      1. 8.2.1 Typical Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Setting Undervoltage and Overvoltage Thresholds
          2. Setting Output Voltage Rise Time (tR)
          3. Setting Power Good Assertion Threshold
          4. Setting Analog Current Monitor Voltage (IMON) Range
        3. Application Curves
    3. 8.3 Active ORing
    4. 8.4 Priority Power MUXing
    5. 8.5 USB PD Port Protection
    6. 8.6 Parallel Operation
  9. Power Supply Recommendations
    1. 9.1 Transient Protection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Reverse Current Protection

The LM73100 functions like an ideal diode and blocks reverse current flow from OUT to IN under all conditions. The device has integrated back-to-back MOSFETs connected in a common drain configuration. The voltage drop between the IN and OUT pins is constantly monitored and the gate drive of the blocking FET (BFET) is adjusted as needed to regulate the forward voltage drop at VFWD. This closed loop regulation scheme enables graceful turn off of the MOSFET during a reverse current event and ensures there's no DC reverse current flow.

The device also uses a conventional comparator (VREVTH) based reverse blocking mechanism to provide fast response to transient reverse currents.Once the device enters reverse current blocking condition, it waits for the (VIN - VOUT) forward drop to exceed the VFWDTH before it performs a fast recovery to reach full forward conduction state. This provides sufficient hysterisis to prevent supply noise or ripple from affecting the reverse current blocking response. The recovery from reverse current blocking is very fast (tSWRCB). This ensures minimum supply droop which is helpful in applications such as power MUX/ORing.

GUID-29736D8E-B7A6-4331-83F7-1BFC943B1018-low.gifFigure 7-6 Reverse Current Blocking Response

The waveforms below illustrate the reverse current blocking performance in various scenarios.

During fast voltage step at output (e.g. hot-plug), the fast comparator based reverse blocking mechanism ensures minimum jump/glitch on the input rail.

GUID-20201207-CA0I-WDB4-GVRG-ZT4V3KH1QG5X-low.png Figure 7-7 Reverse Current Blocking Performance During Fast Voltage Step at Output

During slow voltage ramp at output, the linear ORing based reverse blocking mechanism ensures there's no DC current flow from OUT to IN, thereby avoiding input rail from getting slowly charged up to output voltage.

GUID-20201207-CA0I-TN07-GMSN-LTXVXXQJRNDZ-low.png Figure 7-8 Reverse Current Blocking Performance During Slow Voltage Ramp at Output

When the input supply droops or gets disconnected while the output storage element (capacitor bank or super capacitor) is charged to the full voltage, the linear ORing scheme minimizes the self-discharge from OUT to IN. This ensures maximum hold-up time for the output storage element in critical power back-up applications.

It also prevents incorrect supply presence indication in applications which sense the input voltage to detect if the supply is connected.

GUID-20201208-CA0I-4KGF-Q4WQ-KHSQFX5L1FF0-low.png Figure 7-9 Reverse Current Blocking Performance During Input Supply Failure