SNVSB12B November   2017  – May 2021 LM73605-Q1 , LM73606-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Synchronous Step-Down Regulator
      2. 8.3.2  Auto Mode and FPWM Mode
      3. 8.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 8.3.4  Adjustable Output Voltage
      5. 8.3.5  Enable and UVLO
      6. 8.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 8.3.7  Soft Start and Voltage Tracking
      8. 8.3.8  Adjustable Switching Frequency
      9. 8.3.9  Frequency Synchronization and Mode Setting
      10. 8.3.10 Internal Compensation and CFF
      11. 8.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 8.3.12 Power-Good and Overvoltage Protection
      13. 8.3.13 Overcurrent and Short-Circuit Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 DCM Mode
        3. 8.4.3.3 PFM Mode
        4. 8.4.3.4 Fault Protection Mode
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout For EMI Reduction
      2. 9.1.2 Ground Plane
      3. 9.1.3 Optimize Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.3 Fixed-Frequency Peak Current-Mode Control

The LM73605-Q1/6-Q1 synchronous switched mode voltage regulator employs fixed frequency peak current mode control with advanced features. The fixed switching frequency is controlled by an internal clock. To get accurate DC load regulation, a voltage feedback loop is implemented to generate peak current command. The HS switch is turned on at the rising edge of the clock. As shown in Figure 8-3, during the HS switch on-time, tON, the SW pin voltage, VSW, swings up to approximately VIN, and the inductor current, IL, increases with a linear slope. The HS switch is turned off when the inductor current reaches the peak current command. During the HS switch off-time, tOFF, the LS switch is turned on. Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltage drop across the LS switch. The LS switch is turned off at the next clock cycle, before the HS switch is turned on. The regulation loop adjusts the peak current command to maintain a constant output voltage.

GUID-34F52DF9-FAA3-42B4-BFEA-72E363129EF5-low.gifFigure 8-3 SW Voltage and Inductor Current Waveforms in CCM

Duty cycle D is defined by the on-time of the HS switch over the switching period:

Equation 6. D = tON / TSW

where

  • TSW = 1 / fSW is the switching period

In an ideal buck converter where losses are ignored, D is proportional to the output voltage and inverse proportional to the input voltage: D = VOUT ⁄ VIN.

When the LM73605-Q1/6-Q1 set to operate in auto mode, the LS switch is turned off when its current reaches zero ampere before the next clock cycle comes. Both HS switch and LS switch are off before the HS switch is turned on at the next clock cycle.