SNVSAH5A September   2017  – May 2020 LM73605 , LM73606

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency versus Load Current VOUT = 5 V, fSW = 500 kHz, Auto Mode
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 System Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Synchronous Step-Down Regulator
      2. 7.3.2  Auto Mode and FPWM Mode
      3. 7.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 7.3.4  Adjustable Output Voltage
      5. 7.3.5  Enable and UVLO
      6. 7.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 7.3.7  Soft Start and Voltage Tracking
      8. 7.3.8  Adjustable Switching Frequency
      9. 7.3.9  Frequency Synchronization and Mode Setting
      10. 7.3.10 Internal Compensation and CFF
      11. 7.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 7.3.12 Power-Good and Overvoltage Protection
      13. 7.3.13 Overcurrent and Short-Circuit Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 DCM Mode
        3. 7.4.3.3 PFM Mode
        4. 7.4.3.4 Fault Protection Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Output Voltage Setpoint
        3. 8.2.2.3  Switching Frequency
        4. 8.2.2.4  Input Capacitors
        5. 8.2.2.5  Inductor Selection
        6. 8.2.2.6  Output Capacitor Selection
        7. 8.2.2.7  Feedforward Capacitor
        8. 8.2.2.8  Bootstrap Capacitors
        9. 8.2.2.9  VCC Capacitor
        10. 8.2.2.10 BIAS
        11. 8.2.2.11 Soft Start
        12. 8.2.2.12 Undervoltage Lockout Setpoint
        13. 8.2.2.13 PGOOD
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layout For EMI Reduction
      2. 10.1.2 Ground Plane
      3. 10.1.3 Optimize Thermal Performance
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Enable and UVLO

The LM73605 and LM73606regulate output voltage when the VCC voltage is higher than the undervoltage lock out (UVLO) level, VCC_UVLO, and the EN voltage is higher than VEN_VOUT_H.

The internal LDO output voltage VCC is turned on when the EN voltage is higher than VEN_VCC_H. The precision enable circuitry is also turned on when VCC is above UVLO. Normal operation of the LM73605 and LM73606 with regulated output voltage is enabled when the EN voltage is greater than VEN_VOUT_H. When the EN voltage is less than VEN_VCC_L, the device is in shutdown mode. The internal dividers make sure VEN_VOUT_H is always higher than VEN_VCC_H.

The EN pin cannot be left floating. The simplest way to enable the operation of the LM73605 and LM73606 is to connect the EN pin to PVIN, which allows self-start-up of the LM73605 and LM73606 when VIN rises. Use of a pullup resistor between PVIN and EN pins helps reduce noise coupling from PVIN pin to the EN pin.

Many applications benefit from employing an enable divider to establish a customized system UVLO. This can be used either for sequencing, system timing requirement, or to reduce the occurrence of deep discharge of a battery power source. Figure 14 shows how to use a resistor divider to set a system UVLO level. An external logic output can also be used to drive the EN pin for system sequencing.

LM73605 LM73606 vin_uvlo_nvsah5.gifFigure 14. System UVLO

With a selected RENT, the RENB can be calculated by:

Equation 10. LM73605 LM73606 eq_UVLOdivider_snvsah5.gif

where

  • VIN_ON_H is the desired supply voltage threshold to turn on this device

Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values add more quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in the hundreds of kΩ range is a good starting point.