SNVSB12B November   2017  – May 2021 LM73605-Q1 , LM73606-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 System Characteristics
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Synchronous Step-Down Regulator
      2. 8.3.2  Auto Mode and FPWM Mode
      3. 8.3.3  Fixed-Frequency Peak Current-Mode Control
      4. 8.3.4  Adjustable Output Voltage
      5. 8.3.5  Enable and UVLO
      6. 8.3.6  Internal LDO, VCC_UVLO, and BIAS Input
      7. 8.3.7  Soft Start and Voltage Tracking
      8. 8.3.8  Adjustable Switching Frequency
      9. 8.3.9  Frequency Synchronization and Mode Setting
      10. 8.3.10 Internal Compensation and CFF
      11. 8.3.11 Bootstrap Capacitor and VBOOT-UVLO
      12. 8.3.12 Power-Good and Overvoltage Protection
      13. 8.3.13 Overcurrent and Short-Circuit Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
        1. 8.4.3.1 CCM Mode
        2. 8.4.3.2 DCM Mode
        3. 8.4.3.3 PFM Mode
        4. 8.4.3.4 Fault Protection Mode
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Layout For EMI Reduction
      2. 9.1.2 Ground Plane
      3. 9.1.3 Optimize Thermal Performance
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Receiving Notification of Documentation Updates
    5. 10.5 Support Resources
    6. 10.6 Support Resources
    7. 10.7 Trademarks
    8. 10.8 Electrostatic Discharge Caution
    9. 10.9 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Internal Compensation and CFF

The LM73605-Q1/6-Q1 internally compensated. The internal compensation is designed such that the loop response is stable over a wide operating frequency and output voltage range. The internal R-C values are 500 kΩ and 30 pF, respectively.

When large resistance value (MΩ) is used for RFBT, the pole formed by an internal parasitic capacitor and RFBT can be low enough to reduce the phase margin. If only low ESR output capacitors (ceramic types) are used for COUT, the control loop can have low phase margin. To provide a phase boost an external feedforward capacitor (CFF) can be added in parallel with RFBT. Choose the CFF capacitor to provide most phase boost at the estimated crossover frequency fX:

Equation 18. GUID-62C48C86-7058-4AB7-B6A5-7B6245F5DAAF-low.gif

where

  • K = 20.27 with LM73605-Q1
  • K = 24.16 with LM73606-Q1

Select COUT so that the fX is no higher than 1/6 of the switching frequency. Typically, fX / fSW = 1/10 to 1/8 provides a good combination of stability and performance.

Place the external feedforward capacitor in parallel with the top resistor divider RFBT when additional phase boost is needed.

GUID-20DE1D35-A319-47EF-9852-96B4928E785A-low.gifFigure 8-14 Feedforward Capacitor for Loop Compensation

The feedforward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency of the control loop to boost phase margin. The zero frequency can be found by Equation 19:

Equation 19. fZ-CFF = 1 / (2π × RFBT × CFF)

An additional pole is also introduced with CFF at the frequency of:

Equation 20. fP-CFF = 1 / (2π × CFF × (RFBT // RFBB))

Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. The zero at fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole at fP-CFF helps maintain proper gain margin at frequency beyond the crossover.

The need of CFF depends on RFBT and COUT. Typically, choose RFBT ≤ 100 kΩ. CFF may not be required, because the internal parasitic pole is at higher frequency. If COUT has larger ESR, and ESR zero fZ-ESR = 1 / (2π × ESR × COUT) is low enough to provide phase boost around the crossover frequency, do not use CFF. Equation 21 was tested for ceramic output capacitors:

Equation 21. GUID-61F67D8D-E5F2-4DF5-956C-78F3FF754F8A-low.gif

The CFF creates a time constant with RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. It can also couple too much transient voltage deviation and falsely trigger PGOOD flag.