SNOSDC2B September   2021  – July 2022 LM74721-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reverse Battery Protection (A, C, GATE)
        1. 8.3.1.1 Input TVS Less Operation: VDS Clamp
      2. 8.3.2 Load Disconnect Switch Control (PD)
      3. 8.3.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      4. 8.3.4 Boost Regulator
    4. 8.4 Shutdown Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Boost Converter Components (C2, C3, L1)
        2. 9.2.2.2 Input and Output Capacitance
        3. 9.2.2.3 Hold-Up Capacitance
        4. 9.2.2.4 MOSFET Selection: Q1
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input Pins A to GND – (VCLAMP + 1) 70 V
Input Pins VS, C to GND –0.3 70
Input Pins VSNS, SW, EN, OV to GND, V(A) > 0 V –0.3 70
Input Pins VSNS, SW, EN, OV to GND, V(A) ≤ 0 V V(A) (70 + V(A))
Input Pins C to GND, V(A) ≤ 0 V –1 (70 + V(A))
Input Pins RTN to GND – (VCLAMP + 1) 0.3
Input Pins IVSNS, ISW  –1 10 mA
Input Pins IEN, IOV,  V(A) > 0 V –1
Input Pins IEN, IOV,   V(A) ≤ 0 V Internally limited
Output Pins CAP to C –0.3 15.9 V
Output Pins CAP to A –0.3 VCLAMP + 15.9
Output Pins GATE to A –0.3 15
Output Pins LX, CAP,  PD to GND –0.3 85
Output to Input Pins C to A –5 VCLAMP
Operating junction temperature, Tj(2) –40 150 °C
Storage temperature, Tstg –40 150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.