The LM76002-Q1/LM76003-Q1 has a built-in power-good flag shown on PGOOD pin to indicate whether the output voltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails. The PGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltage below 12 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical range of pullup resistor value is 10 kΩ to 100 kΩ. When the FB voltage is outside the power-good band, +10% above and –10% below the internal reference VREF typically, the PGOOD switch is turned on, and the PGOOD pin voltage is pulled to ground. When the FB is 2% (typical) closer to FB than the PGOOD threshold, the PGOOD switch is turned off, and the pin is pulled up to the voltage connected to the pullup resistor. Both rising and falling edges of the power-good flag have a built-in 220-µs (typical) deglitch delay. To pull up PGOOD pin to a voltage higher than 15V, a resistor divider can be used to divide the voltage down.
For given pullup voltage VPU and desired voltage on PGOOD pin is VPG and with RPGT chosen, value for RPGB can be calculated using Equation 14: