SNOS674G November   1997  – April 2020 LMC6482

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Rail-to-Rail Input
      2.      Rail-to-Rail Output
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for V+ = 5 V
    6. 6.6 Electrical Characteristics for V+ = 3 V
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Amplifier Topology
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 Rail-to-Rail Output
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Upgrading Applications
      2. 8.1.2 Data Acquisition Systems
      3. 8.1.3 Instrumentation Circuits
      4. 8.1.4 Spice Macromodel
    2. 8.2 Typical Applications
      1. 8.2.1 3-V Single-Supply Buffer Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Capacitive Load Compensation
          2. 8.2.1.2.2 Capacitive Load Tolerance
          3. 8.2.1.2.3 Compensating For Input Capacitance
          4. 8.2.1.2.4 Offset Voltage Adjustment
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Single-Supply Applications
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Common-Mode Voltage Range

Unlike Bi-FET amplifier designs, the LMC6482 does not exhibit phase inversion when an input voltage exceeds the negative supply voltage. Figure 53 shows an input voltage exceeding both supplies with no resulting phase inversion on the output.

LMC6482 01171310.png
An input voltage signal exceeds the lMC6482 power supply voltages with no output phase inversion.
Figure 53. Input Voltage

The absolute maximum input voltage is 300 mV beyond either supply rail at room temperature. Voltages greatly exceeding this absolute maximum rating, as in Figure 54, can cause excessive current to flow in or out of the input pins possibly affecting reliability.

LMC6482 01171339.png

NOTE:

A ±7.5-V input signal greatly exceeds the 3-V supply in Figure 55 causing no phase inversion due to RI.
Figure 54. Input Signal

Applications that exceed this rating must externally limit the maximum input current to ±5 mA with an input resistor (RI) as shown in Figure 55.

LMC6482 01171311.png

NOTE:

RI input current protection for voltages exceeding the supply voltages.
Figure 55. RI Input Current Protection for
Voltages Exceeding the Supply Voltages