SNOS674G November   1997  – April 2020 LMC6482

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Rail-to-Rail Input
      2.      Rail-to-Rail Output
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for V+ = 5 V
    6. 6.6 Electrical Characteristics for V+ = 3 V
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Amplifier Topology
      2. 7.3.2 Input Common-Mode Voltage Range
      3. 7.3.3 Rail-to-Rail Output
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Upgrading Applications
      2. 8.1.2 Data Acquisition Systems
      3. 8.1.3 Instrumentation Circuits
      4. 8.1.4 Spice Macromodel
    2. 8.2 Typical Applications
      1. 8.2.1 3-V Single-Supply Buffer Circuit
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Capacitive Load Compensation
          2. 8.2.1.2.2 Capacitive Load Tolerance
          3. 8.2.1.2.3 Compensating For Input Capacitance
          4. 8.2.1.2.4 Offset Voltage Adjustment
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Typical Single-Supply Applications
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at VS = 15 V, single supply, and TA = 25°C (unless otherwise specified)
LMC6482 01171340.pngFigure 1. Supply Current vs Supply Voltage
LMC6482 01171342.pngFigure 3. Sourcing Current vs Output Voltage
LMC6482 01171344.pngFigure 5. Sourcing Current vs Output Voltage
LMC6482 01171346.pngFigure 7. Sinking Current vs Output Voltage
LMC6482 01171348.pngFigure 9. Output Voltage Swing vs Supply Voltage
LMC6482 01171350.pngFigure 11. Input Voltage Noise vs Input Voltage
LMC6482 01171352.pngFigure 13. Input Voltage Noise vs Input Voltage
LMC6482 01171354.pngFigure 15. Crosstalk Rejection vs Frequency
LMC6482 01171356.pngFigure 17. Negative PSRR vs Frequency
LMC6482 01171358.pngFigure 19. CMRR vs Input Voltage
LMC6482 01171360.pngFigure 21. CMRR vs Input Voltage
LMC6482 01171362.pngFigure 23. ΔvOS vs CMR
LMC6482 01171364.pngFigure 25. Input Voltage vs Output Voltage
LMC6482 01171366.pngFigure 27. Open-Loop Frequency Response
LMC6482 01171368.pngFigure 29. Maximum Output Swing vs Frequency
LMC6482 01171370.pngFigure 31. Gain and Phase vs Capacitive Load
LMC6482 01171372.pngFigure 33. Open-Loop Output Impedance vs Frequency
LMC6482 01171374.pngFigure 35. Noninverting Large Signal Pulse Response
LMC6482 01171376.pngFigure 37. Noninverting Large Signal Pulse Response
LMC6482 01171378.pngFigure 39. Noninverting Small Signal Pulse Response
LMC6482 01171380.pngFigure 41. Inverting Large Signal Pulse Response
LMC6482 01171382.pngFigure 43. Inverting Large Signal Pulse Response
LMC6482 01171384.pngFigure 45. Inverting Small Signal Pulse Response
LMC6482 01171386.pngFigure 47. Stability vs Capacitive Load
LMC6482 01171388.pngFigure 49. Stability vs Capacitive Load
LMC6482 01171390.pngFigure 51. Stability vs Capacitive Load
LMC6482 01171341.pngFigure 2. Input Current vs Temperature
LMC6482 01171343.pngFigure 4. Sourcing Current vs Output Voltage
LMC6482 01171345.pngFigure 6. Sinking Current vs Output Voltage
LMC6482 01171347.pngFigure 8. Sinking Current vs Output Voltage
LMC6482 01171349.pngFigure 10. Input Voltage Noise vs Frequency
LMC6482 01171351.pngFigure 12. Input Voltage Noise vs Input Voltage
LMC6482 01171353.pngFigure 14. Crosstalk Rejection vs Frequency
LMC6482 01171355.pngFigure 16. Positive PSRR vs Frequency
LMC6482 01171357.pngFigure 18. CMRR vs Frequency
LMC6482 01171359.pngFigure 20. CMRR vs Input Voltage
LMC6482 01171361.pngFigure 22. ΔvOS vs CMR
LMC6482 01171363.pngFigure 24. Input Voltage vs Output Voltage
LMC6482 01171365.pngFigure 26. Open-Loop Frequency Response
LMC6482 01171367.pngFigure 28. Open-Loop Frequency Response vs Temperature
LMC6482 01171369.pngFigure 30. Gain and Phase vs Capacitive Load
LMC6482 01171371.pngFigure 32. Open-Loop Output Impedance vs Frequency
LMC6482 01171373.pngFigure 34. Slew Rate vs Supply Voltage
LMC6482 01171375.pngFigure 36. Noninverting Large Signal Pulse Response
LMC6482 01171377.pngFigure 38. Noninverting Small Signal Pulse Response
LMC6482 01171379.pngFigure 40. Noninverting Small Signal Pulse Response
LMC6482 01171381.pngFigure 42. Inverting Large Signal Pulse Response
LMC6482 01171383.pngFigure 44. Inverting Small Signal Pulse Response
LMC6482 01171385.pngFigure 46. Inverting Small Signal Pulse Response
LMC6482 01171387.pngFigure 48. Stability vs Capacitive Load
LMC6482 01171389.pngFigure 50. Stability vs Capacitive Load
LMC6482 01171391.pngFigure 52. Stability vs Capacitive Load