SBOSAL2 September   1999  – January 2025 LMC7101

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics for VS = ±1.35V or 2.7V
    6. 5.6  Electrical Characteristics for VS = ±1.5V or 3V
    7. 5.7  Electrical Characteristics for VS = ±2.5V or 5V
    8. 5.8  Electrical Characteristics for VS = ±7.5V or 15V
    9. 5.9  Typical Characteristics for VS = 2.7V
    10. 5.10 Typical Characteristics for VS = 3V
    11. 5.11 Typical Characteristics for VS = 5V
    12. 5.12 Typical Characteristics for VS = 15V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Benefits of the LMC7101 Tiny Amplifier
        1. 6.3.1.1 Size
        2. 6.3.1.2 Height
        3. 6.3.1.3 Signal Integrity
        4. 6.3.1.4 Simplified Board Layout
        5. 6.3.1.5 Low THD
        6. 6.3.1.6 Low Supply Current
        7. 6.3.1.7 Wide Voltage Range
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input Common Mode
        1. 6.4.1.1 Input Common-Mode Voltage Range
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Rail-to-Rail Output
      2. 7.1.2 Capacitive Load Tolerance
      3. 7.1.3 Compensating for Input Capacitance When Using Large Value Feedback Resistors
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Revision History

Changes from Revision SNOS719G (September 2015) to Revision * (January 2025)

  • Moved LMC7101 commercial device from SNOS719G data sheet into new SBOSAL2 data sheetGo
  • Updated Features Go
  • Deleted machine model (MM) in ESD Ratings Go
  • Updated Thermal Information Go
  • Updated parameter names and table format in all Electrical Characteristics Go
  • Added missing temperature range for input offset voltage drift in all Electrical Characteristics Go
  • Changed power-supply rejection ratio from 50dB to 45dB for LMC7101AGo
  • Changed power-supply rejection ratio from 50dB to 45dB for LMC7101AGo
  • Changed input common-mode voltage condition from CMRR ≥ 50dB to CMRR ≥ 47dBGo
  • Changed CMRR MIN from 50dB to 47dB for LMC7101B and from 55dB to 47dB for LMC7101AGo
  • Deleted notes 1 and 2 in all Electrical Characteristics Go
  • Updated note 3 to move information into slew rate test conditionsGo
  • Changed input common-mode voltage condition from CMRR > 50dB to CMRR > 47dBGo
  • Changed CMRR MIN from 60dB to 47dB for LMC7101B and from 64dB to 47dB for LMC7101AGo
  • Added missing quiescent current per amplifier TYP valueGo
  • Changed CMRR TYP from 82dB to 75dBGo
  • Changed CMRR MIN from 60dB to 52dB for LMC7101B and from 65dB to 52dB for LMC7101AGo
  • Changed CMRR MIN for TJ = –40°C to +85°C from 55dB to 51dB for LMC7101B and from 60dB to 51dB for LMC7101AGo
  • Changed CMRR TYP for TJ = –40C to +85C from 82dB to 74dBGo
  • Changed input offset voltage TYP from 0.11mV to 0.26mVGo
  • Changed CMRR MIN from 65dB to 62dB for LMC7101B and from 70dB to 62dB for LMC7101AGo
  • Changed CMRR MIN for TJ = –40°C to +85°C from 65dB to 60dB LMC7101AGo
  • Deleted note 3 and included information to open-loop voltage gain test conditionsGo
  • Deleted Figures 6, 11, 14, 17, 20, 23, and 37Go
  • Added Figure 5-6Go
  • Added Figures 5-21 and 5-25Go