SNOSDI8A May   2024  – November 2025 LMG2650

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 GaN Power FET Switching Parameters
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN Power FET Switching Capability
      2. 7.3.2  Turn-On Slew-Rate Control
      3. 7.3.3  Current-Sense Emulation
      4. 7.3.4  Bootstrap Diode Function
      5. 7.3.5  Input Control Pins (EN, INL, INH, GDH)
      6. 7.3.6  INL - INH Interlock
      7. 7.3.7  AUX Supply Pin
        1. 7.3.7.1 AUX Power-On Reset
        2. 7.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 7.3.8  BST Supply Pin
        1. 7.3.8.1 BST Power-On Reset
        2. 7.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 7.3.9  Overcurrent Protection
      10. 7.3.10 Overtemperature Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 LLC Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 AHB Application
      3. 8.2.3 Motor Drives Application
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Solder-Joint Stress Relief
        2. 8.4.1.2 Signal-Ground Connection
        3. 8.4.1.3 CS Pin Signal
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5 Input Control Pins (EN, INL, INH, GDH)

The EN pin is referenced to AGND and is used to toggle the device between the active and standby modes described in Section 7.4.

The INL pin is referenced to AGND and is used to turn the low-side GaN power FET on and off.

The INH pin is referenced to AGND and is used to turn the high-side GaN power FET on and off. The INH pin is compatible with controllers that use a low-side referenced gate drive signal to control the high-side GaN power FET.

The GDH pin is referenced to SW and is used to turn the high-side GaN power FET on and off. The GDH pin is compatible with controllers that use a high-side referenced signal to control the high-side GaN power FET.

The LMG2650 is intended to be used with either the INH pin or the GDH pin controlling the high-side GaN power FET. Short the unused pin to the reference of the pin (INH to AGND or GDH to SW).

The input control pins have a typical 1V input-voltage-threshold hysteresis for noise immunity. The pins also have a typical 400kΩ pull-down resistance to protect against floating inputs. The 400kΩ saturates for typical input voltages above 4V to limit the maximum input pull-down current to a typical 10uA. There are individual forward based ESD diodes from the EN, INL, and INH pins to the AUX pin. Avoid driving the EN, INL, and INH voltages higher than the AUX voltage. There is also a forward based ESD diode from the GDH pin to the BST pin. Avoid driving the GDH-to-SW voltage higher than the BST-to-SW voltage.

The following conditions block the INL turn-on action:

  • Standby mode (as set by the EN pin above)
  • INH in control of the INL/INH interlock
  • AUX under-voltage lockout (UVLO)
  • Low-side overtemperature protection
  • Low-side GaN Power FET overcurrent protection

The following conditions block the INH turn-on action:

  • Standby mode (as set by the EN pin above)
  • INL in control of the INL/INH interlock
  • AUX UVLO
  • Low-side overtemperature protection
  • BST UVLO
  • High-side overcurrent protection

The following conditions block the GDH turn-on action:

  • BST UVLO
  • High-side overtemperature protection
  • High-side overcurrent protection

Note that the low-side temperature protection blocks the INH pin while the high-side temperature protection blocks the GDH pin.

All the blocking conditions except the INL/INH interlock and the overcurrent protection act independently of the INL, INH, or GDH logic state. Figure 7-3 shows the operation of these control-input independent blocking conditions.


LMG2650 Control-Input-Independent Blocking Condition Operation

Figure 7-3 Control-Input-Independent Blocking Condition Operation

The INL/INH Interlock blocking action is described in Section 7.3.6. Meanwhile, the overcurrent protection blocking action only asserts after the control input turns on the respective GaN power FET of the control input. See Section 7.3.9 for the details.