The gate drive loop impedance must also be minimized to yield strong performance. Although the gate driver is integrated on package, the bypass capacitance for the driver is placed externally on the PCB board. As the GaN device is turned off to a negative voltage, the impedance of the negative source is included in the crucial turn-off path. As the critical hold-off path passes through this external bypass capacitor attached to VNEG, this capacitor must be located close to the LMG341xR070. In the Figure 19, VNEG bypass capacitors C9 and C26 are located immediately adjacent to the pins on the IC with a direct connection to the SOURCE pin.
The bypass capacitors for the input supply (C8 and C23) and the 5V regulator (C5 and C7) must also be located immediately next to the IC with a close connection to the ground plane.