The power loop, comprising the two devices in the half bridge and the high-voltage bus capacitance, undergoes large di/dt during switching events. By minimizing the inductance of this loop, ringing and electro-magnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.
This loop inductance is minimized by locating the power devices as close together as possible. The bus capacitance is positioned in line with the two devices, either below the low-side device or above the high-side device, on the same side of the PCB. The return path (PGND in this case) is located on the second layer on the PCB in close proximity to the top layer. By using an inner layer and not the bottom layer, the vertical dimension of the loop is reduced, thus minimizing inductance. A large number of vias near both the device terminal and bus capacitance carries the high-frequency switching current to the inner layer while minimizing impedance.