SNOSDA8C October   2020  – February 2024 LMG3422R050 , LMG3426R050

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Switching Parameters
      1. 6.1.1 Turn-On Times
      2. 6.1.2 Turn-Off Times
      3. 6.1.3 Drain-Source Turn-On Slew Rate
      4. 6.1.4 Turn-On and Turn-Off Switching Energy
      5. 6.1.5 Zero-Voltage Detection Times
    2. 6.2 Safe Operation Area (SOA)
      1. 6.2.1 Repetitive SOA
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 LMG3422R050 Functional Block Diagram
      2. 7.2.2 LMG3426R050 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  GaN FET Operation Definitions
      2. 7.3.2  Direct-Drive GaN Architecture
      3. 7.3.3  Drain-Source Voltage Capability
      4. 7.3.4  Internal Buck-Boost DC-DC Converter
      5. 7.3.5  VDD Bias Supply
      6. 7.3.6  Auxiliary LDO
      7. 7.3.7  Fault Protection
        1. 7.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 7.3.7.2 Overtemperature Shutdown Protection
        3. 7.3.7.3 UVLO Protection
        4. 7.3.7.4 High-Impedance RDRV Pin Protection
        5. 7.3.7.5 Fault Reporting
      8. 7.3.8  Drive-Strength Adjustment
      9. 7.3.9  Temperature-Sensing Output
      10. 7.3.10 Ideal-Diode Mode Operation
        1. 7.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
      11. 7.3.11 Zero-Voltage Detection (ZVD)
    4. 7.4 Start-Up Sequence
    5. 7.5 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Slew Rate Selection
        2. 8.2.2.2 Signal Level-Shifting
        3. 8.2.2.3 Buck-Boost Converter Design
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Using an Isolated Power Supply
      2. 8.4.2 Using a Bootstrap Diode
        1. 8.4.2.1 Diode Selection
        2. 8.4.2.2 Managing the Bootstrap Voltage
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Solder-Joint Reliability
        2. 8.5.1.2 Power-Loop Inductance
        3. 8.5.1.3 Signal-Ground Connection
        4. 8.5.1.4 Bypass Capacitors
        5. 8.5.1.5 Switch-Node Capacitance
        6. 8.5.1.6 Signal Integrity
        7. 8.5.1.7 High-Voltage Spacing
        8. 8.5.1.8 Thermal Recommendations
      2. 8.5.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Export Control Notice
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • RQZ|54
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

Unless otherwise noted: voltage, resistance, capacitance, and inductance are respect to GND; –40℃ ≤ TJ ≤ 125℃;
VDS = 480V; 9V ≤ VVDD ≤ 18V; VIN = 0V; RDRV connected to LDO5V; LBBSW = 4.7µH
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING TIMES
td(on)(Idrain) Drain-current turn-on delay time From VIN > VIN,IT+ to ID > 1A, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2        28 42 ns
td(on) Turn-on delay time From VIN > VIN,IT+ to VDS < 320V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2        32 52 ns
tr(on) Turn-on rise time From VDS < 320V to VDS < 80V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2        2.5 4 ns
td(off) Turn-off delay time  From VIN < VIN,IT– to VDS > 80V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2        44 65 ns
tf(off) Turn-off fall time(1) From VDS > 80V to VDS > 320V, VBUS = 400V, LHB current = 10A, see Figure 6-1 and Figure 6-2        21 ns
Minimum IN high pulse-width for FET turn-on VIN rise/fall times < 1ns, VDS falls to < 200V, VBUS = 400V, LHB current = 10A, see Figure 6-1   24 ns
STARTUP TIMES
t(start) Driver start-up time From VVDD > VVDD,T+(UVLO) to FAULT high, CLDO5V = 100nF, CVNEG = 2.2µF at 0V bias linearly decreasing to 1.5µF at 15V bias 310 470 us
FAULT TIMES
toff(OC) Overcurrent fault FET turn-off time, FET on before overcurrent VIN = 5V, From ID > IT(OC) to ID < 50A, ID di/dt = 100A/µs 110 145 ns
toff(SC) Short-circuit current fault FET turn-off time, FET on before short circuit VIN = 5V, From ID > IT(SC) to ID < 50A, ID di/dt = 700A/µs 65 100 ns
Overcurrent fault FET turn-off time, FET turning on into overcurrent From ID > IT(OC) to ID < 50A 200 250 ns
Short-circuit fault FET turn-off time, FET turning on into short circuit From ID > IT(SC) to ID < 50A 100 180 ns
IN reset time to clear FAULT latch From VIN < VIN,IT– to FAULT high 250 380 580 us
t(window)(OC) Overcurrent fault to short-circuit fault window time 50 ns
IDEAL-DIODE MODE CONTROL TIMES 
Overtemperature-shutdown ideal-diode mode IN falling blanking time  150 230 360 ns
ZERO VOLTAGE DETECTION TIMES
tWD_ZVD ZVD Pulse Width See Figure 6-3 75 100 140 ns
tDL_ZVD Time delay between IN rise to ZVD pulse's rising edge See Figure 6-3 15 30 ns
t3rd_ZVD 3rd quadrant conduction time when the ZVD pulse starts to appear Vbus = 10V, IL = 5A, Rdrv = 5V, measure the 3rd quadrant conduction time when the ZVD pulse starts to appear. See Figure 6-3 42 56 ns
(1) During turn-off, VDS rise time is the result of the resonance of COSS and loop inductance as well as load current.