SNOSDG2A march   2023  – april 2023 LMG3526R030

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Switching Parameters
      1. 7.1.1 Turn-On Times
      2. 7.1.2 Turn-Off Times
      3. 7.1.3 Drain-Source Turn-On Slew Rate
      4. 7.1.4 Zero-Voltage Detection Times
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN FET Operation Definitions
      2. 8.3.2  Direct-Drive GaN Architecture
      3. 8.3.3  Drain-Source Voltage Capability
      4. 8.3.4  Internal Buck-Boost DC-DC Converter
      5. 8.3.5  VDD Bias Supply
      6. 8.3.6  Auxiliary LDO
      7. 8.3.7  Fault Detection
        1. 8.3.7.1 Overcurrent Protection and Short-Circuit Protection
        2. 8.3.7.2 Overtemperature Shutdown
        3. 8.3.7.3 UVLO Protection
        4. 8.3.7.4 Fault Reporting
      8. 8.3.8  Drive-Strength Adjustment
      9. 8.3.9  Temperature-Sensing Output
      10. 8.3.10 Ideal-Diode Mode Operation
        1. 8.3.10.1 Overtemperature-Shutdown Ideal-Diode Mode
      11. 8.3.11 Zero-Voltage Detection (ZVD)
    4. 8.4 Start-Up Sequence
    5. 8.5 Safe Operation Area (SOA)
      1. 8.5.1 Repetitive SOA
    6. 8.6 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Slew Rate Selection
          1. 9.2.2.1.1 Start-Up and Slew Rate With Bootstrap High-Side Supply
        2. 9.2.2.2 Signal Level-Shifting
        3. 9.2.2.3 Buck-Boost Converter Design
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Using an Isolated Power Supply
      2. 9.4.2 Using a Bootstrap Diode
        1. 9.4.2.1 Diode Selection
        2. 9.4.2.2 Managing the Bootstrap Voltage
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
        1. 9.5.1.1 Solder-Joint Reliability
        2. 9.5.1.2 Power-Loop Inductance
        3. 9.5.1.3 Signal-Ground Connection
        4. 9.5.1.4 Bypass Capacitors
        5. 9.5.1.5 Switch-Node Capacitance
        6. 9.5.1.6 Signal Integrity
        7. 9.5.1.7 High-Voltage Spacing
        8. 9.5.1.8 Thermal Recommendations
      2. 9.5.2 Layout Examples
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Export Control Notice
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.5.1.2 Power-Loop Inductance

The power loop, comprising of the two devices in the half bridge and the high-voltage bus capacitance, undergoes high di/dt during switching events. By minimizing the inductance of this loop, ringing and electromagnetic interference (EMI) can be reduced, as well as reducing voltage stress on the devices.

Place the power devices as close as possible to minimize the power loop inductance. The decoupling capacitors are positioned in line with the two devices. They can be placed close to either device. In Layout Examples, the devices are placed on the bottom layer and the decoupling capacitors are placed on the top layer. The PGND is placed on the top layer, the HVBUS is located on top and third layer, and the switching node is on the top layer. They are connected to the power devices on bottom layer with vias. Area of traces close to the devices are minimized by bottom layer in order to keep clearance between heatsink and conductors.

The power loop inductance can be estimated based on the ringing frequency fring of the drain-source voltage switching waveform based on the following equation:

Equation 1. Lpl=14π2fring2Cring

where Cring is equal to COSS at the bus voltage (refer to Figure 6-8 for the typical value) plus the drain-source parasitic capacitance from the board and load inductor or transformer.

As the parasitic capacitance of load components is hard to character, it is recommended to capture the VDS switching waveform without load components to estimate the power loop inductance. Typically, the power loop inductance of the Layout Example is around 2.5 nH.