SBOS709A July   2016  – July 2016 LMH2832

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: SPI
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Setup Diagrams
    2. 8.2 ATE Testing and DC Measurements
    3. 8.3 Frequency Response
    4. 8.4 Distortion
    5. 8.5 Noise Figure
    6. 8.6 Pulse Response, Slew Rate, and Overdrive Recovery
    7. 8.7 Power-Down
    8. 8.8 Crosstalk, Gain Matching, and Phase Matching
    9. 8.9 Output Measurement Reference Points
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input Characteristics
      2. 9.3.2 Analog Output Characteristics
      3. 9.3.3 Driving Low Insertion-Loss Filters
      4. 9.3.4 Input Impedance Matching
      5. 9.3.5 Power-On Reset (POR)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down (PD)
      2. 9.4.2 Gain Control
    5. 9.5 Programming
      1. 9.5.1 Details of the Serial Interface
      2. 9.5.2 Timing Diagrams
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1 SW Reset Register (address = 2)
      2. 9.6.2 Power-Down Control Register (address = 3)
      3. 9.6.3 Channel A RW0 Register (address = 4)
      4. 9.6.4 Channel A RW1 Register (address = 5)
      5. 9.6.5 Channel B RW0 Register (address = 6)
      6. 9.6.6 Channel B RW1 Register (address = 7)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driving ADCs
        1. 10.1.1.1 SNR Considerations
        2. 10.1.1.2 SFDR Considerations
        3. 10.1.1.3 ADC Input Common-Mode Voltage Considerations (AC-Coupled Input)
        4. 10.1.1.4 ADC Input Common-Mode Voltage Considerations (DC-Coupled Input)
    2. 10.2 Typical Applications
      1. 10.2.1 DOCSIS 3.X Driver
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Source Resistance Matching
          2. 10.2.1.2.2 Output Impedance Matching
          3. 10.2.1.2.3 Voltage Headroom Considerations
        3. 10.2.1.3 Application Curve
      2. 10.2.2 IQ Receiver
    3. 10.3 Do's and Don'ts
      1. 10.3.1 Do:
      2. 10.3.2 Don't:
  11. 11Power Supply Recommendations
    1. 11.1 Split Supplies
    2. 11.2 Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Dual-Channel, Individual SPI™-Controlled DVGA
  • Single 5-V Supply
  • –3-dB Bandwidth: 1.1 GHz (Max Gain)
  • Flat Bandwidth Response: 300 MHz
  • Channel-to-Channel Gain Matching: ±0.05 dB
  • Channel-to-Channel Phase Matching: ±0.1°
  • Gain:
    • 30 dB to –9 dB
    • 1-dB Steps ±0.2 dB
  • Output Third-Order Intercept Point (OIP3):
    • 43 dBm at 300 MHz
    • 51 dBm at 200 MHz
  • Noise Figure (NF):
    • 6.5 dB (Max Gain) at 300 MHz, ZIN = 150 Ω
  • Adjustable Power Consumption:
    • 90 mA to 108 mA per Channel
  • Power-Saving, Power-Down Feature:
    • IQ < 4.5 mA per Channel
    • Power-Down Pin and SPI Programmability
  • Input Return Loss at 300 MHz:
    • 17 dB (RS = 150 Ω)

2 Applications

  • DOCSIS 3.1 CMTS Upstream Direct Sampling Receivers
  • CATV Modem Signal Scaling
  • Programmable Gain IF Amplifiers
  • Generic RF, IF Gain Stages
  • ADC Drivers

3 Description

The LMH2832 is a high-linearity, dual-channel, digital variable-gain amplifier (DVGA) for high-speed signal chain and data-acquisition systems. The LMH2832 is optimized to provide high bandwidth, low distortion, and low noise, thus making the device ideally suited as a dual, 14-bit, analog-to-digital converter (ADC) driver. The device consists of one fixed-gain block and one variable attenuator consisting of a total gain of 30 dB with a maximum attenuation of 39 dB. The gain range is from 30 dB to –9 dB in 1-dB gain steps with a gain accuracy of ±0.2 dB. The input impedance can be easily matched to 50-Ω or 75-Ω systems using a 1:3-Ω or 1:2-Ω ratio balun, respectively. The LMH2832 is designed to drive general-purpose ADCs and also meets the requirements for both data over cable service interface specification (DOCSIS) 3.0 32 quadrature amplitude modulation (QAM) carriers and DOCSIS 3.1 wideband orthogonal frequency-division multiplexing (OFDM) systems. With excellent NF (6.5 dB) and linearity, the LMH2832 is designed to perform to within DOCSIS specifications. The quiescent current in the power-down state is less than 5 mA per channel with the typical current consumption during operation at 105 mA per channel.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
LMH2832 VQFN (40) 6.00 mm × 6.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Output Third-Order Intercept Point (OIP3) Performance

LMH2832 D005_SBOS709.gif