SNAS579G March   2012  – December 2014 LMK00105

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Diagrams
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Vdd and Vddo Power Supplies
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Selection of Clock Input
          1. 7.3.2.1.1 CLKin/CLKin* Pins
          2. 7.3.2.1.2 OSCin/OSCout Pins
      3. 7.3.3 Clock Outputs
        1. 7.3.3.1 Output Enable Pin
        2. 7.3.3.2 Using Less than Five Outputs
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Clock Inputs
      2. 8.1.2 Clock Outputs
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Block Diagram
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Crystal Interface
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Filtering
    2. 9.2 Power Supply Ripple Rejection
    3. 9.3 Power Supply Bypassing
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Ground Planes
      2. 10.1.2 Power Supply Pins
      3. 10.1.3 Differential Input Termination
      4. 10.1.4 Output Termination
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Differential Voltage Measurement Terminology
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from F Revision (May 2013) to G Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

Changes from E Revision (February 2013) to F Revision

  • Added device name to title of document.Go
  • Changed all LLP and QFN packages to WQFN throughout document.Go
  • Deleted optional from CLKin* pin description. And changed complimentary to complementary.Go
  • Added max limit to Output Skew parameter and added tablenote to parameter in Electrical Characteristics Table.Go
  • Changed typical value for both conditions of Propagation Delay in the Electrical Characteristics Table.Go
  • Added Min/Max limits to both conditions of Propagation Delay parameter in Electrical Characteristics Table.Go
  • Changed unit value for the first condition of Part-to-part Skew from ps to ns in the Electrical Characteristics Table.Go
  • Changed both Max values of each Part-to-part Skew condition in Electrical Characteristics Table.Go
  • Changed the Typ value of each Rise/Fall Time condition in the Electrical Characteristics Table. Go
  • Deleted VIL table note.Go
  • Added VI_SE parameter and spec limits with corresponding table note to Electrical Characteristics Table.Go
  • Added CLKin* column to CLKin Input vs. Output States table. Also added fourth row starting with Logic Low under CLKin column.Go
  • Changed table title from CLKin input vs. Output States to OSCin Input vs. Output StatesGo
  • Changed third paragraph in Driving the Clock Inputs section to include CLKin* and LVCMOS text. Removed extra references to other figures. Revised to better correspond with information in Electrical Characteristics Table.Go
  • Deleted Figure 10 (Near End termination) and Figure 11 (Far End termination) from Driving the Clock Inputs sectionGo
  • Changed bypass cap text to signal attenuation text of the fourth paragraph in Driving the Clock Inputs section.Go
  • Changed Single-Ended LVCMOS Input, DC Coupling with Common Mode Biasing image with revised graphic.Go
  • Deleted sentence in reference to two deleted images.Go
  • Changed link from National packaging site to TI packaging site.Go