SNAS635F December   2013  – August 2025 LMK00334

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements, Propagation Delay, and Output Skew
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Crystal Power Dissipation vs RLIM
      2. 7.3.2 Clock Inputs
      3. 7.3.3 Clock Outputs
        1. 7.3.3.1 Reference Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC and VCCO Power Supplies
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Driving the Clock Inputs
        2. 8.2.1.2 Crystal Interface
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Termination and Use of Clock Drivers
        2. 8.2.2.2 Termination for DC-Coupled Differential Operation
        3. 8.2.2.3 Termination for AC-Coupled Differential Operation
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Current Consumption and Power Dissipation Calculations
        1. 8.3.1.1 Power Dissipation Example: Worst-Case Dissipation
      2. 8.3.2 Power Supply Bypassing
        1. 8.3.2.1 Power Supply Ripple Rejection
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Management
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.1 Driving the Clock Inputs

The LMK00334 has two universal inputs (CLKin0/CLKin0* and CLKin1/CLKin1*) that can accept DC-coupled, 3.3V or 2.5V LVPECL, LVDS, CML, SSTL, and other differential and single-ended signals that meet the input requirements specified in Electrical Characteristics. The device can accept a wide range of signals because of the wide input common-mode voltage range (VCM ) and input voltage swing (VID) / dynamic range. For 50% duty cycle and DC-balanced signals, AC coupling can also be employed to shift the input signal to within the VCM range. Refer to Termination and Use of Clock Drivers for signal interfacing and termination techniques.

To achieve the best possible phase noise and jitter performance, the input must have a high slew rate of 3V/ns (differential) or higher. Driving the input with a lower slew rate degrades the noise floor and jitter. For this reason, a differential signal input is recommended over single-ended because differential signal input typically provides higher slew rate and common-mode rejection. Refer to the Noise Floor vs. CLKin Slew Rate and RMS Jitter vs. CLKin Slew Rate plots in Typical Characteristics.

While TI recommends driving the CLKin/CLKin* pair with a differential signal input, driving the pair with a single-ended clock is possible if the clock conforms to the single-ended input specifications for CLKin pins listed in the Electrical Characteristics. For large single-ended input signals, such as 3.3V or 2.5V LVCMOS, a 50Ω load resistor must be placed near the input for signal attenuation to prevent input overdrive as well as for line termination to minimize reflections. Again, the single-ended input slew rate must be as high as possible to minimize performance degradation. The CLKin input has an internal bias voltage of about 1.4V, so the input can be AC coupled as shown in Figure 8-2. The output impedance of the LVCMOS driver plus Rs must be close to 50Ω to match the characteristic impedance of the transmission line and load termination.

LMK00334 Single-Ended LVCMOS Input, AC CouplingFigure 8-2 Single-Ended LVCMOS Input, AC Coupling

A single-ended clock can also be DC-coupled to CLKinX as shown in Figure 8-3. A 50Ω load resistor must be placed near the CLKin input for signal attenuation and line termination. Because half of the single-ended swing of the driver (VO,PP / 2) drives CLKinX, CLKinX* must be externally biased to the midpoint voltage of the attenuated input swing ((VO,PP / 2) × 0.5). The external bias voltage must be within the specified input common voltage (VCM) range. This can be achieved using external biasing resistors in the kΩ range (RB1 and RB2) or another low-noise voltage reference. This verifies that the input swing crosses the threshold voltage at a point where the input slew rate is the highest.

LMK00334 Single-Ended LVCMOS Input, DC Coupling With Common-Mode BiasingFigure 8-3 Single-Ended LVCMOS Input, DC Coupling With Common-Mode Biasing

If the crystal oscillator circuit is not used, driving the OSCin input with an single-ended external clock as shown in Figure 8-4 is possible. The input clock must be AC-coupled to the OSCin pin, which has an internally-generated input bias voltage, and the OSCout pin must be left floating. While OSCin provides an alternative input to multiplex an external clock, TI recommends using either universal input (CLKinX) because those inputs offers higher operating frequency, better common-mode and power supply noise rejection, and greater performance over supply voltage and temperature variations.

LMK00334 Driving OSCin With a Single-Ended InputFigure 8-4 Driving OSCin With a Single-Ended Input