SNAS668D August   2015  – April 2018 LMK03328

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      LMK03328 Simplified Block Diagram
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Thermal Information
    6. 8.6  Electrical Characteristics - Power Supply
    7. 8.7  Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    8. 8.8  Non-Pullable Crystal Characteristics (SECREF_P, SECREF_N)
    9. 8.9  Clock Input Characteristics (PRIREF_P/PRIREF_N, SECREF_P/SECREF_N)
    10. 8.10 VCO Characteristics
    11. 8.11 PLL Characteristics
    12. 8.12 1.8-V LVCMOS Output Characteristics (OUT[7:0])
    13. 8.13 LVCMOS Output Characteristics (STATUS[1:0]
    14. 8.14 Open-Drain Output Characteristics (STATUS[1:0])
    15. 8.15 AC-LVPECL Output Characteristics
    16. 8.16 AC-LVDS Output Characteristics
    17. 8.17 AC-CML Output Characteristics
    18. 8.18 HCSL Output Characteristics
    19. 8.19 Power-On/Reset Characteristics
    20. 8.20 2-Level Logic Input Characteristics (HW_SW_CTRL, PDN, GPIO[5:0])
    21. 8.21 3-Level Logic Input Characteristics (REFSEL, GPIO[3:1])
    22. 8.22 Analog Input Characteristics (GPIO[5])
    23. 8.23 I2C-Compatible Interface Characteristics (SDA, SCL)
    24. 8.24 Typical 156.25-MHz, Closed-Loop Output Phase Noise Characteristics
    25. 8.25 Typical 161.1328125-MHz, Closed-Loop Output Phase Noise Characteristics
    26. 8.26 Closed-Loop Output Jitter Characteristics
    27. 8.27 PCIe Clock Output Jitter
    28. 8.28 Typical Power Supply Noise Rejection Characteristics
    29. 8.29 Typical Power Supply Noise Rejection Characteristics
    30. 8.30 Typical Closed-Loop Output Spur Characteristics
    31. 8.31 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Test Configurations
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Device Block-Level Description
      2. 10.3.2 Device Configuration Control
        1. 10.3.2.1 Hard Pin Mode (HW_SW_CTRL = 1)
          1. 10.3.2.1.1 PLL Blocks
          2. 10.3.2.1.2 Output Buffer Auto Mute
          3. 10.3.2.1.3 Input Block
          4. 10.3.2.1.4 Channel Mux
          5. 10.3.2.1.5 Output Divider
          6. 10.3.2.1.6 Output Driver Format
          7. 10.3.2.1.7 Status MUX, Divider and Slew Rate
        2. 10.3.2.2 Soft Pin Programming Mode (HW_SW_CTRL = 0)
          1. 10.3.2.2.1 Device Config Space
          2. 10.3.2.2.2 PLL Blocks
          3. 10.3.2.2.3 Output Buffer Auto Mute
          4. 10.3.2.2.4 Input Block
          5. 10.3.2.2.5 Channel Mux
          6. 10.3.2.2.6 Output Divider
          7. 10.3.2.2.7 Output Driver Format
          8. 10.3.2.2.8 Status MUX, Divider and Slew Rate
        3. 10.3.2.3 Register File Reference Convention
    4. 10.4 Device Functional Modes
      1. 10.4.1  Smart Input MUX
      2. 10.4.2  Universal Input Buffer (PRI_REF, SEC_REF)
      3. 10.4.3  Crystal Input Interface (SEC_REF)
      4. 10.4.4  Reference Doubler
      5. 10.4.5  Reference Divider (R)
      6. 10.4.6  Input Divider (M)
      7. 10.4.7  Feedback Divider (N)
      8. 10.4.8  Phase Frequency Detector (PFD)
      9. 10.4.9  Charge Pump
      10. 10.4.10 Loop Filter
      11. 10.4.11 VCO Calibration
      12. 10.4.12 Fractional Circuitry
        1. 10.4.12.1 Programmable Dithering Levels
        2. 10.4.12.2 Programmable Delta Sigma Modulator Order
      13. 10.4.13 Post Divider
      14. 10.4.14 High-Speed Output MUX
      15. 10.4.15 High-Speed Output Divider
      16. 10.4.16 High-Speed Clock Outputs
      17. 10.4.17 Output Synchronization
      18. 10.4.18 Status Outputs
        1. 10.4.18.1 Loss of Reference
        2. 10.4.18.2 Loss of Lock
    5. 10.5 Programming
      1. 10.5.1 I2C Serial Interface
      2. 10.5.2 Block Register Write
      3. 10.5.3 Block Register Read
      4. 10.5.4 Write SRAM
      5. 10.5.5 Write EEPROM
      6. 10.5.6 Read SRAM
      7. 10.5.7 Read EEPROM
      8. 10.5.8 Read ROM
      9. 10.5.9 Default Device Configurations in EEPROM and ROM
    6. 10.6 Register Maps
      1. 10.6.1   VNDRID_BY1 Register; R0
      2. 10.6.2   VNDRID_BY0 Register; R1
      3. 10.6.3   PRODID Register; R2
      4. 10.6.4   REVID Register; R3
      5. 10.6.5   PARTID Register; R4
      6. 10.6.6   PINMODE_SW Register; R8
      7. 10.6.7   PINMODE_HW Register; R9
      8. 10.6.8   SLAVEADR Register; R10
      9. 10.6.9   EEREV Register; R11
      10. 10.6.10  DEV_CTL Register; R12
      11. 10.6.11  INT_LIVE Register; R13
      12. 10.6.12  INT_MASK Register; R14
      13. 10.6.13  INT_FLAG_POL Register; R15
      14. 10.6.14  INT_FLAG Register; R16
      15. 10.6.15  INTCTL Register; R17
      16. 10.6.16  OSCCTL2 Register; R18
      17. 10.6.17  STATCTL Register; R19
      18. 10.6.18  MUTELVL1 Register; R20
      19. 10.6.19  MUTELVL2 Register; R21
      20. 10.6.20  OUT_MUTE Register; R22
      21. 10.6.21  STATUS_MUTE Register; R23
      22. 10.6.22  DYN_DLY Register; R24
      23. 10.6.23  REFDETCTL Register; R25
      24. 10.6.24  STAT0_INT Register; R27
      25. 10.6.25  STAT1 Register; R28
      26. 10.6.26  OSCCTL1 Register; R29
      27. 10.6.27  PWDN Register; R30
      28. 10.6.28  OUTCTL_0 Register; R31
      29. 10.6.29  OUTCTL_1 Register; R32
      30. 10.6.30  OUTDIV_0_1 Register; R33
      31. 10.6.31  OUTCTL_2 Register; R34
      32. 10.6.32  OUTCTL_3 Register; R35
      33. 10.6.33  OUTDIV_2_3 Register; R36
      34. 10.6.34  OUTCTL_4 Register; R37
      35. 10.6.35  OUTDIV_4 Register; R38
      36. 10.6.36  OUTCTL_5 Register; R39
      37. 10.6.37  OUTDIV_5 Register; R40
      38. 10.6.38  OUTCTL_6 Register; R41
      39. 10.6.39  OUTDIV_6 Register; R42
      40. 10.6.40  OUTCTL_7 Register; R43
      41. 10.6.41  OUTDIV_7 Register; R44
      42. 10.6.42  CMOSDIVCTRL Register; R45
      43. 10.6.43  CMOSDIV0 Register; R46
      44. 10.6.44  CMOSDIV1 Register; R47
      45. 10.6.45  STATUS_SLEW Register; R49
      46. 10.6.46  IPCLKSEL Register; R50
      47. 10.6.47  IPCLKCTL Register; R51
      48. 10.6.48  PLL1_RDIV Register; R52
      49. 10.6.49  PLL1_MDIV Register; R53
      50. 10.6.50  PLL2_RDIV Register; R54
      51. 10.6.51  PLL2_MDIV Register; R55
      52. 10.6.52  PLL1_CTRL0 Register; R56
      53. 10.6.53  PLL1_CTRL1 Register; R57
      54. 10.6.54  PLL1_NDIV_BY1 Register; R58
      55. 10.6.55  PLL1_NDIV_BY0 Register; R59
      56. 10.6.56  PLL1_FRACNUM_BY2 Register; R60
      57. 10.6.57  PLL1_FRACNUM_BY1 Register; R61
      58. 10.6.58  PLL1_FRACNUM_BY0 Register; R62
      59. 10.6.59  PLL_FRACDEN_BY2 Register; R63
      60. 10.6.60  PLL1_FRACDEN_BY1 Register; R64
      61. 10.6.61  PLL1_FRACDEN_BY0 Register; R65
      62. 10.6.62  PLL1_MASHCTRL Register; R66
      63. 10.6.63  PLL1_LF_R2 Register; R67
      64. 10.6.64  PLL1_LF_C1 Register; R68
      65. 10.6.65  PLL1_LF_R3 Register; R69
      66. 10.6.66  PLL1_LF_C3 Register; R70
      67. 10.6.67  PLL2_CTRL0 Register; R71
      68. 10.6.68  PLL2_CTRL1 Register; R72
      69. 10.6.69  PLL2_NDIV_BY1 Register; R73
      70. 10.6.70  PLL2_NDIV_BY0 Register; R74
      71. 10.6.71  PLL2_FRACNUM_BY2 Register; R75
      72. 10.6.72  PLL2_FRACNUM_BY1 Register; R76
      73. 10.6.73  PLL2_FRACNUM_BY0 Register; R77
      74. 10.6.74  PLL2_FRACDEN_BY2 Register; R78
      75. 10.6.75  PLL2_FRACDEN_BY1 Register; R79
      76. 10.6.76  PLL2_FRACDEN_BY0 Register; R80
      77. 10.6.77  PLL2_MASHCTRL Register; R81
      78. 10.6.78  PLL2_LF_R2 Register; R82
      79. 10.6.79  PLL2_LF_C1 Register; R83
      80. 10.6.80  PLL2_LF_R3 Register; R84
      81. 10.6.81  PLL2_LF_C3 Register; R85
      82. 10.6.82  XO_MARGINING Register; R86
      83. 10.6.83  XO_OFFSET_GPIO5_STEP_1_BY1 Register; R88
      84. 10.6.84  XO_OFFSET_GPIO5_STEP_1_BY0 Register; R89
      85. 10.6.85  XO_OFFSET_GPIO5_STEP_2_BY1 Register; R90
      86. 10.6.86  XO_OFFSET_GPIO5_STEP_2_BY0 Register; R91
      87. 10.6.87  XO_OFFSET_GPIO5_STEP_3_BY1 Register; R92
      88. 10.6.88  XO_OFFSET_GPIO5_STEP_3_BY0 Register; R93
      89. 10.6.89  XO_OFFSET_GPIO5_STEP_4_BY1 Register; R94
      90. 10.6.90  XO_OFFSET_GPIO5_STEP_4_BY0 Register; R95
      91. 10.6.91  XO_OFFSET_GPIO5_STEP_5_BY1 Register; R96
      92. 10.6.92  XO_OFFSET_GPIO5_STEP_5_BY0 Register; R97
      93. 10.6.93  XO_OFFSET_GPIO5_STEP_6_BY1 Register; R98
      94. 10.6.94  XO_OFFSET_GPIO5_STEP_6_BY0 Register; R99
      95. 10.6.95  XO_OFFSET_GPIO5_STEP_7_BY1 Register; R100
      96. 10.6.96  XO_OFFSET_GPIO5_STEP_7_BY0 Register; R101
      97. 10.6.97  XO_OFFSET_GPIO5_STEP_8_BY1 Register; R102
      98. 10.6.98  XO_OFFSET_GPIO5_STEP_8_BY0 Register; R103
      99. 10.6.99  XO_OFFSET_SW_BY1 Register; R104
      100. 10.6.100 XO_OFFSET_SW_BY0 Register; R105
      101. 10.6.101 PLL1_CTRL2 Register; R117
      102. 10.6.102 PLL1_CTRL3 Register; R118
      103. 10.6.103 PLL1_CALCTRL0 Register; R119
      104. 10.6.104 PLL1_CALCTRL1 Register; R120
      105. 10.6.105 PLL2_CTRL2 Register; R131
      106. 10.6.106 PLL2_CTRL3 Register; R132
      107. 10.6.107 PLL2_CALCTRL0 Register; R133
      108. 10.6.108 PLL2_CALCTRL1 Register; R134
      109. 10.6.109 NVMCNT Register; R136
      110. 10.6.110 NVMCTL Register; R137
      111. 10.6.111 NVMLCRC Register; R138
      112. 10.6.112 MEMADR_BY1 Register; R139
      113. 10.6.113 MEMADR_BY0 Register; R140
      114. 10.6.114 NVMDAT Register; R141
      115. 10.6.115 RAMDAT Register; R142
      116. 10.6.116 ROMDAT Register; R143
      117. 10.6.117 NVMUNLK Register; R144
      118. 10.6.118 REGCOMMIT_PAGE Register; R145
      119. 10.6.119 XOCAPCTRL_BY1 Register; R199
      120. 10.6.120 XOCAPCTRL_BY0 Register; R200
    7. 10.7 EEPROM Map
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Application Block Diagram Examples
      2. 11.2.2 Jitter Considerations in Serdes Systems
      3. 11.2.3 Frequency Margining
        1. 11.2.3.1 Fine Frequency Margining
        2. 11.2.3.2 Coarse Frequency Margining
      4. 11.2.4 Design Requirements
        1. 11.2.4.1 Detailed Design Procedure
          1. 11.2.4.1.1 Device Selection
            1. 11.2.4.1.1.1 Calculation Using LCM
          2. 11.2.4.1.2 Device Configuration
          3. 11.2.4.1.3 PLL Loop Filter Design
            1. 11.2.4.1.3.1 PLL Loop Filter Design
          4. 11.2.4.1.4 PLL and Clock Output Assignment
      5. 11.2.5 Spur Mitigation Techniques
        1. 11.2.5.1 Phase Detector Spurs
        2. 11.2.5.2 Integer Boundary Fractional Spurs
        3. 11.2.5.3 Primary Fractional Spurs
        4. 11.2.5.4 Sub-Fractional Spurs
  12. 12Power Supply Recommendations
    1. 12.1 Device Power Up Sequence
    2. 12.2 Device Power Up Timing
    3. 12.3 Power Down
    4. 12.4 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
      1. 12.4.1 Mixing Supplies
      2. 12.4.2 Power-On Reset
      3. 12.4.3 Powering Up From Single-Supply Rail
      4. 12.4.4 Powering Up From Split-Supply Rails
      5. 12.4.5 Slow Power-Up Supply Ramp
      6. 12.4.6 Non-Monotonic Power-Up Supply Ramp
      7. 12.4.7 Slow Reference Input Clock Start-Up
    5. 12.5 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Ensure Thermal Reliability
      2. 13.1.2 Support for PCB Temperature up to 105°C
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Community Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11.2.2 Jitter Considerations in Serdes Systems

Jitter-sensitive applications such as 10-Gbps or 100-Gbps Ethernet, deploy a serial link using a Serializer in the transmit section (TX) and a De serializer in the receive section (RX). These SERDES blocks are typically embedded in an ASIC or FPGA. Estimating the clock jitter impact on the link budget requires understanding of the TX PLL bandwidth and the RX CDR bandwidth.

As can be seen in Figure 82, the pass band region between the TX low pass cutoff and RX high pass cutoff frequencies is the range over which the reference clock jitter adds without any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate the reference clock jitter with a 20 dB/dec or even steeper roll-off. Modern ASIC or FPGA designs have some flexibility on deciding the optimal RX CDR bandwidth and TX PLL bandwidth. These bandwidths are typically set based on what is achievable in the ASIC or FPGA process node, without increasing design complexity, and on any jitter tolerance or wander specification that needs to be met, as related to the RX CDR bandwidth.

The overall allowable jitter in a serial link is dictated by IEEE or other relevant standards. For example, IEEE802.3ba states that the maximum transmit jitter (peak-peak) for 10-Gbps Ethernet should be no more than 0.28 × UI and this equates to a 27.1516 ps, p-p for the overall allowable transmit jitter.

The jitter contributing elements are made up of the reference clock, generated potentially from a device like LMK03328, the transmit medium, transmit driver and so forth. Only a portion of the overall allowable transmit jitter is allocated to the reference clock, typically 20% or lower. Therefore, the allowable reference clock jitter for a 20% clock jitter budget is 5.43 ps, p-p.

Jitter in a reference clock is made up of deterministic jitter (arising from spurious signals due to supply noise or mixing from other outputs or from the reference input) and random jitter (usually due to thermal noise and other uncorrelated noise sources). A typical clock tree in a serial link system consists of clock generators and fanout buffers. The allowable reference clock jitter of 5.43 ps, p-p is needed at the output of the fanout buffer. Modern fanout buffers have low additive random jitter (less than 100 fs, rms) with no substantial contribution to the deterministic jitter. Therefore, the clock generator and fanout buffer contribute to the random jitter while the primary contributor to the deterministic jitter is the clock generator. Rule of thumb, for modern clock generators, is to allocate 25% of allowable reference clock jitter to the deterministic jitter and 75% to the random jitter. This amounts to an allowable deterministic jitter of 1.36 ps, p-p and an allowable random jitter of 4.07 ps, p-p. For serial link systems that need to meet a BER of 10–12, the allowable random jitter in root-mean square is 0.29 ps, rms. This is calculated by dividing the p-p jitter by 14 for a BER of 10–12. Accounting for random jitter from the fanout buffer, the random jitter needed from the clock generator is 0.27 ps, rms. This is calculated by the root-mean square subtraction from the desired jitter at the fanout buffer's output assuming 100 fs, rms of additive jitter from the fanout buffer.

With careful frequency planning techniques, like spur optimization (covered in the Spur Mitigation Techniques section) and on-chip LDOs to suppress supply noise, the LMK03328 is able to generate clock outputs with deterministic jitter that is below 1 ps, p-p and random jitter that is below 0.2 ps, rms. This gives the serial link system with additional margin on the allowable transmit jitter resulting in a BER better than 10–12.

LMK03328 dependence_of_clock_jitter_serial_links_snas668.gifFigure 82. Dependence of Clock Jitter in Serial Links