SNAS668D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
NO. | NAME | TYPE | DESCRIPTION |
---|---|---|---|
POWER | |||
— | DAP | Ground | Die Attach Pad.
The DAP is an electrical connection and provides a thermal dissipation path. For proper electrical and thermal performance of the device, a 6x6 via pattern (0.3-mm holes) is recommended to connect the DAP to PCB ground layers. Refer to Layout Guidelines. |
4 | VDD_DIG | Analog | 3.3-V Power Supply for Digital Control and STATUS outputs. |
5 | VDD_IN | Analog | 3.3-V Power Supply for Input Block. |
18 | VDDO_01 | Analog | 1.8-V, 2.5-V, 3.3-V Power Supply for OUT0/OUT1 channel. |
19 | VDDO_23 | Analog | 1.8-V, 2.5-V, 3.3-V Power Supply for OUT2/OUT3 channel. |
27 | VDD_PLL2 | Analog | 3.3-V Power Supply for PLL2. |
36 | VDD_PLL1 | Analog | 3.3-V Power Supply for PLL1. |
37 | VDDO_4 | Analog | 1.8-V, 2.5-V, 3.3-V Power Supply for OUT4 channel. |
40 | VDDO_5 | Analog | 1.8-V, 2.5-V, 3.3-V Power Supply for OUT5 channel. |
43 | VDDO_6 | Analog | 1.8-V, 2.5-V, 3.3-V Power Supply for OUT6 channel. |
46 | VDDO_7 | Analog | 1.8-V, 2.5-V, 3.3-V Power Supply for OUT7 channel. |
INPUT BLOCK | |||
6, 7 | PRIREF_P,
PRIREF_N |
Universal | Primary reference clock.
Accepts a differential or single-ended input. Input pins have AC-coupling capacitors and biasing internally. For LVCMOS input, the non-driven input pin should be pulled down to ground. |
8 | REFSEL | LVCMOS | Manual reference input selection for PLL1 and PLL2 (3-state).
Weak pullup resistor. |
9 | HW_SW_CTRL | LVCMOS | Selection for Hard Pin Mode (ROM), Soft Pin Mode (EEPROM), or Register Default Mode.
Weak pullup resistor. |
10, 11 | SECREF_P,
SECREF_N |
Universal | Secondary reference clock.
Accepts a differential or single-ended input or Crystal input. Input pins have AC-coupling capacitors and biasing internally. For LVCMOS input, external input termination is needed to attenuate the swing to less than 2.6 V, and the non-driven input pin should be pulled down to ground. For crystal input, AT cut fundamental crystal should be used as per defined spec and pullable crystal should be used for fine margining. |
SYNTHESIZER BLOCK | |||
3 | CAP_DIG | Analog | External Bypass Capacitor for digital blocks. Attach a 10 µF to GND. |
28 | CAP_PLL2 | Analog | External Bypass Capacitor for PLL2. Attach a 10 µF to GND. |
29 | LF2 | Analog | External Loop Filter for PLL2. |
34 | LF1 | Analog | External Loop Filter for PLL1. |
35 | CAP_PLL1 | Analog | External Bypass Capacitor for PLL1. Attach a 10 µF to GND. |
OUTPUT BLOCK | |||
14, 15 | OUT0_P,
OUT0_N |
Universal | Differential/LVCMOS Output Pair 0. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
17, 16 | OUT1_P,
OUT1_N |
Universal | Differential/LVCMOS Output Pair 1. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
20, 21 | OUT2_P,
OUT2_N |
Universal | Differential/LVCMOS Output Pair 2. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
23, 22 | OUT3_P,
OUT3_N |
Universal | Differential/LVCMOS Output Pair 3. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
39, 38 | OUT4_P,
OUT4_N |
Universal | Differential/LVCMOS Output Pair 4. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
42, 41 | OUT5_P,
OUT5_N |
Universal | Differential/LVCMOS Output Pair 5. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
45, 44 | OUT6_P,
OUT6_N |
Universal | Differential/LVCMOS Output Pair 6. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
48, 47 | OUT7_P,
OUT7_N |
Universal | Differential/LVCMOS Output Pair 7. Programmable driver with differential or 2x 1.8-V LVCMOS outputs. |
DIGITAL CONTROL / INTERFACES(1) | |||
1 | STATUS0 | Universal | Status Output 0 (open-drain, requires external pullup) or 3.3-V LVCMOS output from synth (push-pull). Status signal selection and output polarity are programmable. |
2 | STATUS1 | Universal | Status Output 1 (open-drain, requires external pullup) or 3.3-V LVCMOS output from synth (push-pull). Status signal selection and output polarity are programmable. |
12 | GPIO0 | LVCMOS | Multifunction Inputs (2-state). |
13 | PDN | LVCMOS | Device Power-down (active low). Weak pullup resistor. |
33 | GPIO5 | Universal | Multifunction Input (2-state) or Analog input for frequency margin. |
24 | GPIO1 | LVCMOS | Multifunction Input (3-state or 2-state). |
25 | SDA | LVCMOS | I2C Serial Data (bidirectional, open-drain). Requires an external pullup resistor to VDD_DIG. I2C slave address is initialized from on-chip EEPROM. |
26 | SCL | LVCMOS | I2C Serial Clock (bidirectional, open-drain). Requires an external pullup resistor to VDD_DIG. |
30 | GPIO2 | LVCMOS | Multifunction Input (3-state or 2-state). |
31 | GPIO3 | LVCMOS | Multifunction Input (3-state or 2-state). |
32 | GPIO4 | LVCMOS | Multifunction Input (2-state). |