SNAS668D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
M Divider for PLL1
Bit # | Field | Type | Reset | EEPROM | Description | |
---|---|---|---|---|---|---|
[7:5] | RESERVED | - | - | N | Reserved. | |
[4:0] | PLL1MDIV[4:0] | RW | 0x00 | Y | PLL1 M Divider. PLL1 M Divider ratio is set by PLL1MDIV. | |
PLL1MDIV | PLL1 M-Divider Value | |||||
0 (0x00) | Bypass | |||||
1 (0x01) | 2 | |||||
... | ... | |||||
31 (0x1F) | 32 |