SNAS668D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The PLL2_CALCTRL1 register is described in the following table.
Bit # | Field | Type | Reset | EEPROM | Description |
---|---|---|---|---|---|
[7:1] | RESERVED | - | - | N | Reserved. |
[0] | PLL2_LOOPBW | RW | 0 | Y | PLL2 Loop bandwidth Control. When PLL2_LOOPBW is 1 the loop bandwidth of PLL2 is reduced to 200 Hz (jitter cleaner mode). When PLL2_LOOPBW is 0 the loop bandwidth of PLL2 is set to its normal range (clock generator mode). NOTE: Proper PLL settings must be used (PFD, charge pump, loop filter) with setting the desired value for PLL2_LOOPBW. |