SNAS668D August 2015 – April 2018 LMK03328
PRODUCTION DATA.
The primary reference can support differential or single-ended clocks. The secondary reference can support differential or single-ended clocks or crystal. The differential input buffers on both primary and secondary support internal 50 Ω to ground or 100-Ω termination between P and N followed by on-chip AC-coupling capacitors to internal self-biased circuitry. Internal biasing is offered before the on-chip AC-coupling capacitors when the clock inputs are AC coupled externally, and this is enabled by setting R29.0 = 1 (for primary reference) or R29.1 = 1 (for secondary reference). When the clock inputs are DC coupled, the internal biasing before the on-chip AC-coupling capacitors is disabled by settings R29.0 = 0 (for primary reference) or R29.1 = 0 (for secondary reference). Figure 45 shows the differential input buffer termination options implemented on both primary and secondary and the switches (SWLVDS, SWHCSL, SWAC) are controlled by R29[5-0]. Table 4 shows the primary and secondary buffer configuration matrix for LVPECL, CML, LVDS, HCSL, and LVCMOS inputs.
R50.5 / R50.7 | R50.4 / R50.6 | R29.4 / R29.5 | R29.2 / R29.3 | R29.0 / R29.1 | MODE | EXTERNAL COUPLING | TERMINATION | BIASING |
---|---|---|---|---|---|---|---|---|
0 | 1 | 0 | 1 | 1 | HCSL | AC | Internal | Internal |
0 | 1 | 0 | 1 | 1 | LVDS | AC | Internal | Internal |
0 | 1 | 0 | 1 | 1 | LVPECL | AC | Internal | Internal |
0 | 1 | 0 | 1 | 1 | CML | AC | Internal | Internal |
0 | 1 | 1 | 0 | 0 | HCSL | DC | Internal | External |
0 | 1 | 0 | 1 | 0 | LVDS | DC | Internal | External |
0 | 1 | 0 | 0 | 0 | LVPECL | DC | External | External |
0 | 1 | 0 | 0 | 0 | CML | DC | External | External |
0 | 0 | 0 | 0 | 0 | LVCMOS | DC | N/A | N/A |
The following figures show recommendations for interfacing LMK03328’s primary or secondary inputs with LVCMOS, LVPECL, LVDS, CML, and HCSL drivers, respectively.
NOTE
The secondary reference accepts up to 2.6-V maximum swing when LVCMOS input option is selected.