SNAS771A December 2018 – December 2018 LMK05318
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
Figure 23 shows the PLL architecture implemented in the LMK05318. The primary "PLL1" channel consists of a digital PLL (DPLL) and analog PLL (APLL1) with integrated BAW VCO (VCO1) capable of generating clocks with RMS phase jitter of 50-fs typical. A secondary APLL (APLL2) with integrated LC VCO (VCO2) can be used as an additional clock generation domain with RMS phase jitter of 125-fs typical.
The DPLL is comprised of a time-to-digital converter (TDC), digital loop filter (DLF), and 40-bit fractional feedback (FB) divider with sigma-delta-modulator (SDM). The APLLs are comprised of a reference (R) divider, phase-frequency detector (PFD), loop filter (LF), fractional feedback (N) divider with SDM, and VCO. APLL2 has a reference selection mux that allows APLL2 to be either locked to APLL1's VCO domain (Cascaded APLL2) or locked to the XO input (Non-Cascaded APLL2). Otherwise, APLL2 can be disabled (powered-down) if this clock domain is not needed. APLL1's VCO feeds the output clock distribution blocks directly, whereas APLL2's VCO drives the clock distribution blocks through its VCO post-dividers.
The following sections describe the basic principle of operation for DPLL mode and APLL-only mode. See PLL Operating Modes for more details on the PLL modes of operation including holdover.