SNAS888A September   2024  – November 2024 LMK1D2102L , LMK1D2104L , LMK1D2106L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Common Mode
      2. 8.3.2 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Enable / Disable and Amplitude Selection
      2. 8.4.2 LVDS Output Termination
      3. 8.4.3 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions


LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L LMK1D2102L: RGT Package 16-Pin VQFN Top View
Figure 5-1 LMK1D2102L: RGT Package 16-Pin VQFN Top View


Figure 5-3 LMK1D2106L: RHA Package 40-Pin VQFN Top View

LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L LMK1D2104L: RHD Package 28-Pin VQFN Top View
Figure 5-2 LMK1D2104L: RHD Package 28-Pin VQFN Top View


Figure 5-4 LMK1D2108L: RGZ Package 48-Pin VQFN Top View
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L
DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT
IN0_P, IN0_N 6, 7 9, 10 9, 8 10, 9 I Primary: Differential input pair or single-ended input
IN1_P, IN1_N 3, 4 5, 6 2, 3 3, 4 I Secondary: Differential input pair or single-ended input
Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.
BANK ENABLE AND AMPLITUDE SELECT
AMP_SELA 2 4 10 11 I Output bank enable/disable with an internal 500kΩ pullup and 320kΩ pulldown; (See Section 8.4.1)
AMP_SELB - - 1 2 I Output bank enable/disable with an internal 500kΩ pullup and 320kΩ pulldown; (See Section 8.4.1)
BIAS VOLTAGE OUTPUT
VAC_REF0 8 11 7 8 O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1µF capacitor to GND on this pin.
VAC_REF1 - - 4 5 O Bias voltage output for capacitive coupled inputs. If used, TI recommends using a 0.1µF capacitor to GND on this pin.
DIFFERENTIAL CLOCK OUTPUT
OUT0_P, OUT0_N 9, 10 12, 13 12, 13 14, 15 O Differential LVDS output pair number 0
OUT1_P, OUT1_N 11, 12 16, 17 14, 15 16, 17 O Differential LVDS output pair number 1
OUT2_P, OUT2_N 13, 14 18, 19 16, 17 18, 19 O Differential LVDS output pair number 2
OUT3_P, OUT3_N 15, 16 20, 21 18, 19 20, 21 O Differential LVDS output pair number 3
OUT4_P, OUT4_N - 22, 23 22, 23 22, 23 O Differential LVDS output pair number 4
OUT5_P, OUT5_N - 24, 25 24, 25 25, 26 O Differential LVDS output pair number 5
OUT6_P, OUT6_N - 26, 27 26, 27 27, 28 O Differential LVDS output pair number 6
OUT7_P, OUT7_N - 2, 3 28, 29 29, 30 O Differential LVDS output pair number 7
OUT8_P, OUT8_N - - 32, 33 31, 32 O Differential LVDS output pair number 8
OUT9_P, OUT9_N - - 34, 35 33, 34 O Differential LVDS output pair number 9
OUT10_P, OUT10_N - - 36, 37 35, 36 O Differential LVDS output pair number 10
OUT11_P, OUT11_N - - 38, 39 38, 39 O Differential LVDS output pair number 11
OUT12_P, OUT12_N - - - 40, 41 O Differential LVDS output pair number 12
OUT13_P, OUT13_N - - - 42, 43 O Differential LVDS output pair number 13
OUT14_P, OUT14_N - - - 44, 45 O Differential LVDS output pair number 14
OUT15_P, OUT15_N - - - 46, 47 O Differential LVDS output pair number 15
SUPPLY VOLTAGE
VDD 5 8, 15, 28 - - P Device power supply (1.8V, 2.5V, or 3.3V) for Bank 0 and Bank 1
VDDA - - 6, 11, 20 7, 13, 24 P Device power supply (1.8V, 2.5V, or 3.3V) for Bank 0
VDDB - - 5, 31, 40 6, 37, 48 P Device power supply (1.8V, 2.5V, or 3.3V) for Bank 1
GROUND
GND 1 1, 14 21, 30 1, 12 G Ground
MISC
DAP DAP DAP DAP DAP G Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for heat dissipation.
(1) G = Ground, I = Input, O = Output, P = Power