SNAS888A September   2024  – November 2024 LMK1D2102L , LMK1D2104L , LMK1D2106L

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Common Mode
      2. 8.3.2 Fail-Safe Input
    4. 8.4 Device Functional Modes
      1. 8.4.1 Output Enable / Disable and Amplitude Selection
      2. 8.4.2 LVDS Output Termination
      3. 8.4.3 Input Termination
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Examples
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGT|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.2 Layout Examples

LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L PCB Layout Example for LMK1D2104L, Top LayerFigure 9-6 PCB Layout Example for LMK1D2104L, Top Layer
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L PCB Layout Example for LMK1D2106L, Top LayerFigure 9-8 PCB Layout Example for LMK1D2106L, Top Layer
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L PCB Layout Example for LMK1D2108L, Top LayerFigure 9-10 PCB Layout Example for LMK1D2108L, Top Layer
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L PCB Layout Example for LMK1D2104L, GND LayerFigure 9-7 PCB Layout Example for LMK1D2104L, GND Layer
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L PCB Layout Example for LMK1D2106L, GND layerFigure 9-9 PCB Layout Example for LMK1D2106L, GND layer
LMK1D2102L LMK1D2104L LMK1D2106L LMK1D2108L PCB Layout Example for LMK1D2108L, GND LayerFigure 9-11 PCB Layout Example for LMK1D2108L, GND Layer