SNAS722A December 2017 – October 2018 LMK61E07
The clock output on LMK61E07 can be configured as LVPECL, LVDS, or HCSL by programming R21[1:0]. Interfacing to LVPECL, LVDS, or HCSL receivers are done either with direct coupling or with AC-coupling capacitor as shown in Figure 16 through Figure 21.
The LVDS output structure has integrated 125 Ω termination between each side (P and N) of the differential pair. The HCSL output structure is open drain and can be DC or AC coupled to HCSL receivers with appropriate termination scheme. The LVPECL output structure is an emitter follower requiring external termination.