SNAS722A December 2017 – October 2018 LMK61E07
The host (DSP, Microcontroller, FPGA, and so forth) configures and monitors the LMK61E07 through the I2C port. The host reads and writes to a collection of control and status bits called the register map. The device blocks can be controlled and monitored through a specific grouping of bits located within the register file. The host controls and monitors certain device Wide critical parameters directly through register control and status bits. In the absence of the host, the LMK61E07 can be configured to operate from its on-chip EEPROM. The EEPROM array is automatically copied to the device registers upon power up. The user has the flexibility to rewrite the contents of EEPROM from the SRAM up to 100 times.
Within the device registers, there are certain bits that have read or write access. Other bits are read-only (an attempt to write to a read-only bit will not change the state of the bit). Certain device registers and bits are reserved meaning that they must not be changed from their default reset state. Figure 26 shows interface and control blocks within LMK61E07 and the arrows refer to read access from and write access to the different embedded memories (EEPROM, SRAM).