SNAS722A December 2017 – October 2018 LMK61E07
The PLL_CTRL1 register provides control of PLL. The PLL_CTRL1 register fields are described in the following table.
|||PLL_D||RW||1||Y||PLL R Divider Frequency Doubler Enable. If PLL_D is 1 the R Divider Frequency Doubler is enabled.|
|[3:0]||PLL_CP[3:0]||RW||0x8||Y||PLL Charge Pump Current. Other combinations of PLL_CP[3:0] not in table below are reserved and not supported.|
|PLL_CP[3:0]||PLL Charge Pump Current|
|4 (0x4)||1.6 mA|
|8 (0x8)||6.4 mA|