SNAS805 June 2020 LMK61E08
PRODUCTION DATA.
The PLL_NDIV_BY0 register is described in the following table.
BIT NO. | FIELD | TYPE | DEFAULT | EEPROM | DESCRIPTION |
---|---|---|---|---|---|
[7:0] | PLL_NDIV[7:0] | RW | 0xDC | Y | PLL N Divider Byte 0. PLL Integer N Divider bits [7:0]. |