SNAS826 April   2022 LMK6C

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 LMK6P/D Thermal Information
    5. 7.5 LMK6C Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Diagrams
  8. 8 Parameter Measurement Information
    1. 8.1 Device Output Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bulk Acoustic Wave (BAW)
      2. 9.3.2 Device Block-Level Description
      3. 9.3.3 Function Pin(s)
      4. 9.3.4 Clock Output Interfacing and Termination
      5. 9.3.5 Temperature Stability
      6. 9.3.6 Mechanical Robustness
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ensuring Thermal Reliability
      2. 12.1.2 Best Practices for Signal Integrity
      3. 12.1.3 Recommended Solder Reflow Profile
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Device Nomenclature
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Packaging Information
    2. 14.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DLF|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.2 Device Block-Level Description

High-Q resonant tank of BAW die is complimented with an ultra-low noise oscillator on a base die, designed in CMOS process node. Temperature variations of oscillation frequency are continuously monitored by a co-located precision temperature sensor. Correction for frequency is done using an advance signal processing algorithm which runs continuously in the background while making use of per part calibration coefficients, stored in NVM, to compensate frequency within ±10 ppm. A very low jitter, low power fractional output divider (FOD) in the frequency correction path allows necessary compensation with minimum impact to the phase jitter while generating a per-programmed output frequency clock. The output driver is capable of providing both single-ended LVCMOS and differential LVPECL and LVDS output formats. Finally, a small power-reset-clock management system consisting of several low noise LDOs and digital controller makes sure noise sensitive modules work with enough isolation while maintaining output clock fidelity.