SNAS826 April   2022 LMK6C

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 LMK6P/D Thermal Information
    5. 7.5 LMK6C Thermal Information
    6. 7.6 Electrical Characteristics
    7. 7.7 Timing Diagrams
  8. 8 Parameter Measurement Information
    1. 8.1 Device Output Configurations
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Bulk Acoustic Wave (BAW)
      2. 9.3.2 Device Block-Level Description
      3. 9.3.3 Function Pin(s)
      4. 9.3.4 Clock Output Interfacing and Termination
      5. 9.3.5 Temperature Stability
      6. 9.3.6 Mechanical Robustness
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Ensuring Thermal Reliability
      2. 12.1.2 Best Practices for Signal Integrity
      3. 12.1.3 Recommended Solder Reflow Profile
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Device Nomenclature
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Packaging Information
    2. 14.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
  • DLF|4
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics

over the parameters listed in the Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption Characteristics
IDD Device Power Consumption LVPECL output, Fout ≤ 200 MHz(1) 60 TBD mA
IDD Device Power Consumption LVPECL output, 200 MHz < Fout ≤ 400 MHz(1) 90 TBD mA
IDD Device Power Consumption LVDS output, Fout ≤ 200 MHz(1) 52 TBD mA
IDD Device Power Consumption LVDS output, 200 MHz < Fout ≤ 400 MHz(1) 80 TBD mA
IDD Device Power Consumption LVCMOS output, Fout  ≤ 200 MHz, CL = No Load 50 TBD mA
IDD-PD Device Power-Down Current OE = GND TBD mA
LVPECL Output Characteristics
Fout Output Frequency 1 400 MHz
VOD Output Voltage Swing (VOH – VOL) AC Load, VDD = 3.3 V 550 650 750 mV
VOD Output Voltage Swing (VOH – VOL) AC Load, VDD = 2.5 V 500 600 700 mV
VOD Output Voltage Swing (VOH – VOL) AC Load, VDD = 1.8 V   325 400 450 mV
VOD Output Voltage Swing (VOH – VOL) DC Load, VDD = 2.5 V/ 3.3 V(2) 700 800 900 mV
VOD Output Voltage Swing (VOH – VOL) DC Load, VDD = 1.8 V(2) 500 600 700 mV
VOD,DIFF Differential Output peak-peak swing 2x|VOD| V
VOS Output Common-Mode Voltage VDD = 3.3 V(2) 1.5 1.6 1.7 V
VDD = 2.5 V(2) 0.825 0.9 0.975 V
VOS Output Common-Mode Voltage VDD = 1.8 V(2) 0.45 0.5 0.55 V
tR/tF Output Rise/Fall Time 20% to 80% of VOD,DIFF 120 200 ps
ODC Output Duty Cycle 45 50 55 %
PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) Fout = 156.25 MHz –158 dBc/Hz
LVDS Output Characteristics
Fout Output Frequency 1 400 MHz
VOD Output Voltage Swing (VOH – VOL) Under LVDS Load condition 250 350 450 mV
VOD,DIFF Differential Output peak-peak swing 2x|VOD| V
VOS Output Common-Mode Voltage VDD = 2.5 V/3.3 V 1.025 1.2 1.375 V
VOS Output Common-Mode Voltage VDD = 1.8 V 0.80 0.9 1.0 V
tR/tF Output Rise/Fall Time 20% to 80% of VOD,DIFF 150 250 ps
ODC Output Duty Cycle 45 50 55 %
PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) Fout = 156.25 MHz –158 dBc/Hz
LVCMOS Output Characteristics
Fout Output Frequency 1 200 MHz
VOL Output Low Voltage IOL = 3.6 mA, VDD = 1.8 V 0.36 V
VOL Output Low Voltage IOL = 5.0 mA, VDD = 2.5 V 0.5 V
IOL = 6.6 mA, VDD = 3.3 V 0.66 V
VOH Output High Voltage IOH = 3.6 mA, VDD = 1.8 V 1.44 V
VOH Output High Voltage IOH = 5.0 mA, VDD = 2.5 V 2 V
IOH = 6.6 mA, VDD = 3.3 V 2.64 V
tR/tF Output Rise/Fall Time 20% to 80% of VOH – VOL, CL = 2 pF 0.5 1 ns
ODC Output Duty Cycle 45 50 55 %
PN-Floor Output Phase Noise Floor (fOFFSET > 10 MHz) Fout = 50 MHz –155 dBc/Hz
Rout Output Impedance 40 50 60 Ω
CL Maximum capacitive load Fout > 50 MHz 15 pF
CL Maximum capacitive load Fout < 50 MHz 30 pF
EN Input Characteristics
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 1.3 V
IIL Input Low Current EN = GND –40 µA
IIH Input High Current EN = VDD 40 µA
CIN Input Capacitance 2 pF
LVPECL and LVDS Frequency Tolerance
FT Total Frequency Stability Inclusive of: solder shift, initial tolerance, variation over –40℃ to 85℃, variation over rated supply voltage range, and 10 year aging at 25℃. ±25 ppm
LVCMOS Frequency Tolerance
FT Total Frequency Stability Inclusive of: solder shift, initial tolerance, variation over –40℃ to 105℃, variation over rated supply voltage range, and 10 year aging at 25℃. ±25 ppm
PSRR Spur induced by 50 mV power supply ripple at 156.25MHz output, VDD = 2.5V/3.3 V Sine wave at 50 kHz –85 dBc
Sine wave at 100 kHz –85 dBc
Sine wave at 500 kHz –85 dBc
Sine wave at 1 MHz –85 dBc
Power-On Characteristics
tSTART_UP Start-up Time Time elapsed from 0.95 × VDD until output is enabled and output is within specification 5 ms
tOE-EN Output Enable Time Time elapsed from OE = VIH until output is enabled and output is within specification, Fout > 10 MHz 25 µs
tOE-DIS Output Disable Time Time elapsed from OE = VIL until output is disabled, Fout > 10 MHz 25 µs
LVPECL - Clock Output Jitter
RJ Random Phase Jitter Fout ≥ 100 MHz, Integration BW: 12 kHz – 20 MHz 100 125 fs
RJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 0.7 ps
RJITT,PK Peak-peak Period Jitter Fout ≥ 25 MHz 7 ps
LVDS - Clock Output Jitter
RJ Random Phase Jitter Fout ≥ 100 MHz, Integration BW: 12 kHz – 20 MHz 100 125 fs
RJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 0.7 ps
RJITT,PK Peak-peak Period Jitter Fout ≥ 25 MHz 7 ps
LVCMOS - Clock Output Jitter
RJ Random Phase Jitter Fout = 24 MHz, Integration BW: 12 kHz – 5 MHz 400 fs
RJ Random Phase Jitter Fout = 156.25 MHz, Integration BW: 12 kHz – 20 MHz 200 500 fs
RJITT,RMS RMS Period Jitter Fout ≥ 25 MHz 0.7 ps
RJITT,PK Peak-peak Period Jitter Fout ≥ 25 MHz 7 ps
(1) Excluding Load current
(2) DC Load condition